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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:Consolas;mso-fareast-language:EN-US">Hi,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:Consolas;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:Consolas;mso-fareast-language:EN-US">You can bounce the numbers, or any questions, off Kai Ji (added).<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:Consolas;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:Consolas;mso-fareast-language:EN-US">John<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:Consolas;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:Consolas;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Patrick Robb <probb@iol.unh.edu>
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<b>Sent:</b> Tuesday, April 8, 2025 6:03 PM<br>
<b>To:</b> Richardson, Bruce <bruce.richardson@intel.com><br>
<b>Cc:</b> Cody Cheng <ccheng@iol.unh.edu>; Dean Marx <dmarx@iol.unh.edu>; Adam Hassick <ahassick@iol.unh.edu>; Nicholas Pratte <npratte@iol.unh.edu>; ci@dpdk.org<br>
<b>Subject:</b> Intel QuickAssist crypto operations testing<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hi Bruce,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Do you remember last year when we had a tech board call about the server refresh at UNH-IOL, you recommended that for the Intel processor DUT system, we get a processor SKU which includes a QAT device? We did this, and the SKU we selected
was Intel(R) Xeon(R) Gold 5415+.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Those devices are QAT 4xxx series QAT 4942 as reported by dpdk-devbind.py --status:<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Crypto devices using kernel driver<br>
==================================<br>
0000:76:00.0 '4xxx Series QAT 4942' numa_node=0 drv=4xxx unused=qat_4xxx,vfio-pci
<br>
0000:f3:00.0 '4xxx Series QAT 4942' numa_node=1 drv=4xxx unused=qat_4xxx,vfio-pci<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Cody has been setting up the testing for this QAT device, which is done via DPDK's test-crypto-perf application. He is satisfied with the metrics the card is getting with DPDK (he compared them against some reports Intel has published and
also what we see on a QAT PCI card on an Ampere ARM system here at UNH). <o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">So, he thinks we are ready to go online. However, in order to be careful, we were wondering if we should run the information we have by an Intel contact first. Is there any DPDK/quickassist/crypto person on your team who could serve as
a contact for this purpose? If so, I think Cody can add them to this thread and share the more detailed info for that person for them to approve (or disapprove). <o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks let me know!<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">-Patrick<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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