[dpdk-dev] [PATCH v3 2/3] crypto/qat: add Kasumi support in Intel(R) QAT driver

De Lara Guarch, Pablo pablo.de.lara.guarch at intel.com
Sat Sep 17 01:13:51 CEST 2016


Hi Deepak,

> -----Original Message-----
> From: Jain, Deepak K
> Sent: Thursday, September 15, 2016 3:04 AM
> To: dev at dpdk.org
> Cc: De Lara Guarch, Pablo; Jain, Deepak K
> Subject: [PATCH v3 2/3] crypto/qat: add Kasumi support in Intel(R) QAT
> driver
> 
> This patch add kasumi support in Intel(R)
> QuickAssist driver.
> 
> Signed-off-by: Deepak Kumar Jain <deepak.k.jain at intel.com>
> ---
>  doc/guides/cryptodevs/qat.rst                    | 10 +--
>  doc/guides/rel_notes/release_16_11.rst           |  2 +-
>  drivers/crypto/qat/qat_adf/qat_algs.h            | 10 ++-
>  drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 72
> +++++++++++++++++++--
>  drivers/crypto/qat/qat_crypto.c                  | 79
> ++++++++++++++++++++++--
>  5 files changed, 158 insertions(+), 15 deletions(-)
> 
> diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
> index 78cadc4..6cdfb93 100644
> --- a/doc/guides/cryptodevs/qat.rst
> +++ b/doc/guides/cryptodevs/qat.rst

...

> +* Snow3g(UEA2) and Kasumi(F8) supported only if cipher length, cipher
> offset fields are byte-aligned.
> +* Snow3g(UIA2) and kasumi(F9) supported only if hash length, hash offset
> fields are byte-aligned.

kasumi -> Kasumi. Actually, it should be KASUMI, and Snow3g should be SNOW 3G.
Will send a patch to fix this in the documentation.

>  * No BSD support as BSD QAT kernel driver not available.
>  * Snow3g (UIA2) not supported in the PMD of **Intel QuickAssist
> Technology C3xxx** device.
> 

...

> diff --git a/drivers/crypto/qat/qat_crypto.c
> b/drivers/crypto/qat/qat_crypto.c
> index bc8d5b1..1bb1dd1 100644
> --- a/drivers/crypto/qat/qat_crypto.c
> +++ b/drivers/crypto/qat/qat_crypto.c
> @@ -387,6 +387,51 @@ static const struct rte_cryptodev_capabilities
> qat_pmd_capabilities[] = {
>  			}, },
>  		}, }
>  	},
> +	{       /* KASUMI (F8) */
> +		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> +		{.sym = {
> +			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
> +			{.cipher = {
> +				.algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
> +				.block_size = 8,
> +				.key_size = {
> +					.min = 16,
> +					.max = 16,
> +					.increment = 0
> +				},
> +				.iv_size = {
> +					.min = 16,
> +					.max = 16,
> +					.increment = 0
> +				}

IV size is 8.

> +			}, }
> +		}, }
> +	},
> +		{       /* KASUMI (F9) */

Remove extra tab before brace up here.

> +		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> +		{.sym = {
> +			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> +			{.auth = {
> +				.algo = RTE_CRYPTO_AUTH_KASUMI_F9,
> +				.block_size = 8,
> +				.key_size = {
> +					.min = 16,
> +					.max = 16,
> +					.increment = 0
> +				},
> +				.digest_size = {
> +					.min = 4,
> +					.max = 4,
> +					.increment = 0
> +				},
> +				.aad_size = {
> +					.min = 8,
> +					.max = 8,
> +					.increment = 0
> +				}
> +			}, }
> +		}, }
> +	},
>  	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
>  };


More information about the dev mailing list