[dpdk-dev] [PATCH 46/61] net/qede/base: add mailbox for resource allocation

Rasesh Mody rasesh.mody at cavium.com
Mon Feb 27 08:57:02 CET 2017


Add the Management FW mailbox for getting non-l2 resource allocation
information.

Signed-off-by: Rasesh Mody <rasesh.mody at cavium.com>
---
 drivers/net/qede/base/ecore.h      |    1 +
 drivers/net/qede/base/ecore_dev.c  |   60 ++++++++++++++++++++++++------------
 drivers/net/qede/base/mcp_public.h |    1 +
 3 files changed, 43 insertions(+), 19 deletions(-)

diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h
index 60a8a6b..25b6c4e 100644
--- a/drivers/net/qede/base/ecore.h
+++ b/drivers/net/qede/base/ecore.h
@@ -291,6 +291,7 @@ enum ecore_resources {
 	ECORE_LL2_QUEUE,
 	ECORE_CMDQS_CQS,
 	ECORE_RDMA_STATS_QUEUE,
+	ECORE_BDQ,
 	ECORE_MAX_RESC,			/* must be last */
 };
 
diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 8385157..113c326 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -2470,6 +2470,9 @@ static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
 	case ECORE_RDMA_STATS_QUEUE:
 		mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
 		break;
+	case ECORE_BDQ:
+		mfw_res_id = RESOURCE_BDQ_E;
+		break;
 	default:
 		break;
 	}
@@ -2477,67 +2480,84 @@ static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
 	return mfw_res_id;
 }
 
-static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
-				      enum ecore_resources res_id)
+static
+enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
+					    enum ecore_resources res_id,
+					    u32 *p_resc_num,
+					    u32 *p_resc_start)
 {
 	u8 num_funcs = p_hwfn->num_funcs_on_engine;
 	bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
 	struct ecore_sb_cnt_info sb_cnt_info;
-	u32 dflt_resc_num = 0;
 
 	switch (res_id) {
 	case ECORE_SB:
 		OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
 		ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
-		dflt_resc_num = sb_cnt_info.sb_cnt;
+		*p_resc_num = sb_cnt_info.sb_cnt;
 		break;
 	case ECORE_L2_QUEUE:
-		dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
+		*p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
 				 MAX_NUM_L2_QUEUES_BB) / num_funcs;
 		break;
 	case ECORE_VPORT:
-		dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
+		*p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
 				 MAX_NUM_VPORTS_BB) / num_funcs;
 		break;
 	case ECORE_RSS_ENG:
-		dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
+		*p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
 				 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
 		break;
 	case ECORE_PQ:
-		dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
+		*p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
 				 MAX_QM_TX_QUEUES_BB) / num_funcs;
 		break;
 	case ECORE_RL:
-		dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
+		*p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
 		break;
 	case ECORE_MAC:
 	case ECORE_VLAN:
 		/* Each VFC resource can accommodate both a MAC and a VLAN */
-		dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
+		*p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
 		break;
 	case ECORE_ILT:
-		dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
+		*p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
 				 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
 		break;
 	case ECORE_LL2_QUEUE:
-		dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
+		*p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
 		break;
 	case ECORE_RDMA_CNQ_RAM:
 	case ECORE_CMDQS_CQS:
 		/* CNQ/CMDQS are the same resource */
 		/* @DPDK */
-		dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
+		*p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
 		break;
 	case ECORE_RDMA_STATS_QUEUE:
 		/* @DPDK */
-		dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
+		*p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
 				 MAX_NUM_VPORTS_BB) / num_funcs;
 		break;
+	case ECORE_BDQ:
+		/* @DPDK */
+		*p_resc_num = 0;
+		break;
+	default:
+		break;
+	}
+
+
+	switch (res_id) {
+	case ECORE_BDQ:
+		if (!*p_resc_num)
+			*p_resc_start = 0;
+		break;
 	default:
+		*p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
 		break;
 	}
 
-	return dflt_resc_num;
+	return ECORE_SUCCESS;
 }
 
 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
@@ -2569,6 +2589,8 @@ static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
 		return "CMDQS_CQS";
 	case ECORE_RDMA_STATS_QUEUE:
 		return "RDMA_STATS_QUEUE";
+	case ECORE_BDQ:
+		return "BDQ";
 	default:
 		return "UNKNOWN_RESOURCE";
 	}
@@ -2586,14 +2608,14 @@ static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
 	p_resc_num = &RESC_NUM(p_hwfn, res_id);
 	p_resc_start = &RESC_START(p_hwfn, res_id);
 
-	dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
-	if (!dflt_resc_num) {
+	rc = ecore_hw_get_dflt_resc(p_hwfn, res_id,
+				    &dflt_resc_num, &dflt_resc_start);
+	if (rc != ECORE_SUCCESS) {
 		DP_ERR(p_hwfn,
 		       "Failed to get default amount for resource %d [%s]\n",
 			res_id, ecore_hw_get_resc_name(res_id));
-		return ECORE_INVAL;
+		return rc;
 	}
-	dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
 
 #ifndef ASIC_ONLY
 	if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h
index 6f0e2f9..333d147 100644
--- a/drivers/net/qede/base/mcp_public.h
+++ b/drivers/net/qede/base/mcp_public.h
@@ -1025,6 +1025,7 @@ enum resource_id_enum {
 	RESOURCE_NUM_RSS_ENGINES_E	=	14,
 	RESOURCE_LL2_QUEUE_E		=	15,
 	RESOURCE_RDMA_STATS_QUEUE_E	=	16,
+	RESOURCE_BDQ_E			=	17,
 	RESOURCE_MAX_NUM,
 	RESOURCE_NUM_INVALID		=	0xFFFFFFFF
 };
-- 
1.7.10.3



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