[dpdk-dev] [disscussion] mlx4 driver MLX4_PMD_TX_MP_CACHE default vaule

[Adrien Mazarguil]

Hi Changhu,

On Fri, Jul 28, 2017 at 10:52:45AM +0000, chenchanghu wrote:
> Hi   Adrien,
> Thanks very much! I have got the  question about MLX4_PMD_TX_MP_CACHE value, we will modify this value to suit our applications.
>   However, in the 2 clients or more clients test, we found that the function 'txq->if_qp->send_pending' and 'txq->if_qp->send_flush(txq->qp)'  in 'mlx4_tx_burst'   probabilistic cost almost *5ms* each function . The probability is about 1/50000, which means every 50000 packets sending appeared once.
>   Does this phenomenon is normal? Or do we ignored some configurations that not showed documented?

5 ms for these function calls is strange and certainly not normal. Are you
sure this time is spent in send_pending()/send_flush() and not in
mlx4_tx_burst() itself?

Given the MP cache size and number of mempools involved in your setup, cache
look-up might be longer than normal, but this alone does not explain it.
Might be something else, such as:

- txq_mp2mr() fails to register a mempool of one of these packets for some
  reason (chunked mempool?) Enable CONFIG_RTE_LIBRTE_MLX4_DEBUG and look
  for "unable to get MP <-> MR association" messages.

- You've enabled TX inline mode using a large value and CPU cycles are
  wasted by the PMD doing memcpy() on large packets. Don't enable inline TX
  (set CONFIG_RTE_LIBRTE_MLX4_MAX_INLINE to 0).

- Sent packets have too many segments (more than MLX4_PMD_SGE_WR_N). This is
  super expensive as the PMD needs to linearize extra segments. You can set
  MLX4_PMD_SGE_WR_N to the next power of two (8), however beware doing so
  will degrade performance.

This might also be caused by external factors that depend on the application
or the host system, if for instance DPDK memory is spread across NUMA
nodes. Make sure it's not the case.

-- 
Adrien Mazarguil
6WIND