[dpdk-dev] [PATCH] net/i40e: fix flexible payload configuration

Xing, Beilei beilei.xing at intel.com
Thu Oct 12 12:13:36 CEST 2017


> -----Original Message-----
> From: Chilikin, Andrey
> Sent: Saturday, October 7, 2017 2:11 AM
> To: dev at dpdk.org
> Cc: Xing, Beilei <beilei.xing at intel.com>; Wu, Jingjing
> <jingjing.wu at intel.com>; Chilikin, Andrey <andrey.chilikin at intel.com>
> Subject: [PATCH] net/i40e: fix flexible payload configuration
> 
> Removed legacy writes to ORT/PIT registers from i40e_GLQF_reg_init(struct
> i40e_hw *hw) function.
> Latest NVM versions contain all relevant values and these values should not
> be overwritten by SW to maintain driver/firmware compatibility and to avoid
> conflicts with dynamic device personalization profiles.
> 
> Signed-off-by: Andrey Chilikin <andrey.chilikin at intel.com>
> ---
>  drivers/net/i40e/i40e_ethdev.c | 23 +++++++++++------------
>  1 file changed, 11 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
> index e2af51c89..d770fc343 100644
> --- a/drivers/net/i40e/i40e_ethdev.c
> +++ b/drivers/net/i40e/i40e_ethdev.c
> @@ -704,23 +704,22 @@ RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "*
> igb_uio | uio_pci_generic | vfio-pci");  static inline void
> i40e_GLQF_reg_init(struct i40e_hw *hw)  {
>  	/*
> -	 * Initialize registers for flexible payload, which should be set by NVM.
> -	 * This should be removed from code once it is fixed in NVM.
> +	 * Force global configuration for flexible payload
> +	 * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
> +	 * This should be removed from code once proper
> +	 * configuration API is added to avoid configuration conflicts
> +	 * between ports of the same device.
>  	 */
> -	I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
> -	I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
> -	I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
> -	I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
>  	I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
>  	I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
>  	I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
> -	I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
> -	I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
> -	I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
> -	I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
> -	I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
> 
> -	/* Initialize registers for parsing packet type of QinQ */
> +	/*
> +	 * Initialize registers for parsing packet type of QinQ
> +	 * This should be removed from code once proper
> +	 * configuration API is added to avoid configuration conflicts
> +	 * between ports of the same device.
> +	 */
>  	I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
>  	I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);  }
> --
> 2.13.0

Acked-by: Beilei Xing <beilei.xing at intel.com>



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