[dpdk-dev] [PATCH 48/80] net/sfc/base: move port config to ef10 NIC board config
Andrew Rybchenko
arybchenko at solarflare.com
Tue Feb 20 08:34:06 CET 2018
From: Andy Moreton <amoreton at solarflare.com>
Signed-off-by: Andy Moreton <amoreton at solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko at solarflare.com>
---
drivers/net/sfc/base/ef10_impl.h | 5 ----
drivers/net/sfc/base/ef10_nic.c | 23 +++++++++++++++++--
drivers/net/sfc/base/hunt_nic.c | 46 +++++++++++--------------------------
drivers/net/sfc/base/medford2_nic.c | 41 ++++++++++-----------------------
drivers/net/sfc/base/medford_nic.c | 44 ++++++++++-------------------------
5 files changed, 58 insertions(+), 101 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index e598a9a..4a50955 100644
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -1175,11 +1175,6 @@ ef10_get_privilege_mask(
__in efx_nic_t *enp,
__out uint32_t *maskp);
-extern __checkReturn efx_rc_t
-ef10_external_port_mapping(
- __in efx_nic_t *enp,
- __in uint32_t port,
- __out uint8_t *external_portp);
#if EFSYS_OPT_RX_PACKED_STREAM
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index b315e9f..c63aad8 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1467,7 +1467,7 @@ static struct ef10_external_port_map_s {
},
};
- __checkReturn efx_rc_t
+static __checkReturn efx_rc_t
ef10_external_port_mapping(
__in efx_nic_t *enp,
__in uint32_t port,
@@ -1546,14 +1546,33 @@ ef10_nic_board_cfg(
__in efx_nic_t *enp)
{
const efx_nic_ops_t *enop = enp->en_enop;
+ efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
+ efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+ uint32_t port;
efx_rc_t rc;
+ /* Get the (zero-based) MCDI port number */
+ if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
+ goto fail1;
+
+ /* EFX MCDI interface uses one-based port numbers */
+ emip->emi_port = port + 1;
+
+ if ((rc = ef10_external_port_mapping(enp, port,
+ &encp->enc_external_port)) != 0)
+ goto fail2;
+
+ /* Get remaining controller-specific board config */
if ((rc = enop->eno_board_cfg(enp)) != 0)
if (rc != EACCES)
- goto fail1;
+ goto fail3;
return (0);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index 903c669..0b311b6 100644
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -76,13 +76,11 @@ hunt_nic_get_required_pcie_bandwidth(
hunt_board_cfg(
__in efx_nic_t *enp)
{
- efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint8_t mac_addr[6] = { 0 };
uint32_t board_type = 0;
ef10_link_state_t els;
efx_port_t *epp = &(enp->en_port);
- uint32_t port;
uint32_t pf;
uint32_t vf;
uint32_t mask;
@@ -102,20 +100,6 @@ hunt_board_cfg(
EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
-
- if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
- goto fail1;
-
- /*
- * NOTE: The MCDI protocol numbers ports from zero.
- * The common code MCDI interface numbers ports from one.
- */
- emip->emi_port = port + 1;
-
- if ((rc = ef10_external_port_mapping(enp, port,
- &encp->enc_external_port)) != 0)
- goto fail2;
-
/*
* Get PCIe function number from firmware (used for
* per-function privilege and dynamic config info).
@@ -123,7 +107,7 @@ hunt_board_cfg(
* - PCIe VF: pf = parent PF, vf = VF number.
*/
if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
- goto fail3;
+ goto fail1;
encp->enc_pf = pf;
encp->enc_vf = vf;
@@ -144,7 +128,7 @@ hunt_board_cfg(
rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
}
if (rc != 0)
- goto fail4;
+ goto fail2;
EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
@@ -155,7 +139,7 @@ hunt_board_cfg(
if (rc == EACCES)
board_type = 0;
else
- goto fail5;
+ goto fail3;
}
encp->enc_board_type = board_type;
@@ -163,11 +147,11 @@ hunt_board_cfg(
/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
- goto fail6;
+ goto fail4;
/* Obtain the default PHY advertised capabilities */
if ((rc = ef10_phy_get_link(enp, &els)) != 0)
- goto fail7;
+ goto fail5;
epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
epp->ep_adv_cap_mask = els.els_adv_cap_mask;
@@ -198,7 +182,7 @@ hunt_board_cfg(
else if ((rc == ENOTSUP) || (rc == ENOENT))
encp->enc_bug35388_workaround = B_FALSE;
else
- goto fail8;
+ goto fail6;
/*
* If the bug41750 workaround is enabled, then do not test interrupts,
@@ -217,7 +201,7 @@ hunt_board_cfg(
} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
encp->enc_bug41750_workaround = B_FALSE;
} else {
- goto fail9;
+ goto fail7;
}
if (EFX_PCI_FUNCTION_IS_VF(encp)) {
/* Interrupt testing does not work for VFs. See bug50084. */
@@ -255,12 +239,12 @@ hunt_board_cfg(
} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
encp->enc_bug26807_workaround = B_FALSE;
} else {
- goto fail10;
+ goto fail8;
}
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
- goto fail11;
+ goto fail9;
/*
* The Huntington timer quantum is 1536 sysclk cycles, documented for
@@ -279,7 +263,7 @@ hunt_board_cfg(
/* Check capabilities of running datapath firmware */
if ((rc = ef10_get_datapath_caps(enp)) != 0)
- goto fail12;
+ goto fail10;
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
@@ -329,13 +313,13 @@ hunt_board_cfg(
* can result in time-of-check/time-of-use bugs.
*/
if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
- goto fail13;
+ goto fail11;
encp->enc_privilege_mask = mask;
/* Get interrupt vector limits */
if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail14;
+ goto fail12;
/* Ignore error (cannot query vector limits from a VF). */
base = 0;
@@ -351,7 +335,7 @@ hunt_board_cfg(
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
- goto fail15;
+ goto fail13;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
/* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -359,10 +343,6 @@ hunt_board_cfg(
return (0);
-fail15:
- EFSYS_PROBE(fail15);
-fail14:
- EFSYS_PROBE(fail14);
fail13:
EFSYS_PROBE(fail13);
fail12:
diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c
index 3bca504..0b0f775 100644
--- a/drivers/net/sfc/base/medford2_nic.c
+++ b/drivers/net/sfc/base/medford2_nic.c
@@ -48,13 +48,11 @@ medford2_nic_get_required_pcie_bandwidth(
medford2_board_cfg(
__in efx_nic_t *enp)
{
- efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint8_t mac_addr[6] = { 0 };
uint32_t board_type = 0;
ef10_link_state_t els;
efx_port_t *epp = &(enp->en_port);
- uint32_t port;
uint32_t pf;
uint32_t vf;
uint32_t mask;
@@ -78,19 +76,6 @@ medford2_board_cfg(
encp->enc_vi_window_shift = vi_window_shift;
- if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
- goto fail1;
-
- /*
- * NOTE: The MCDI protocol numbers ports from zero.
- * The common code MCDI interface numbers ports from one.
- */
- emip->emi_port = port + 1;
-
- if ((rc = ef10_external_port_mapping(enp, port,
- &encp->enc_external_port)) != 0)
- goto fail2;
-
/*
* Get PCIe function number from firmware (used for
* per-function privilege and dynamic config info).
@@ -98,7 +83,7 @@ medford2_board_cfg(
* - PCIe VF: pf = parent PF, vf = VF number.
*/
if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
- goto fail3;
+ goto fail2;
encp->enc_pf = pf;
encp->enc_vf = vf;
@@ -127,7 +112,7 @@ medford2_board_cfg(
rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
}
if (rc != 0)
- goto fail4;
+ goto fail3;
EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
@@ -138,7 +123,7 @@ medford2_board_cfg(
if (rc == EACCES)
board_type = 0;
else
- goto fail5;
+ goto fail4;
}
encp->enc_board_type = board_type;
@@ -146,11 +131,11 @@ medford2_board_cfg(
/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
- goto fail6;
+ goto fail5;
/* Obtain the default PHY advertised capabilities */
if ((rc = ef10_phy_get_link(enp, &els)) != 0)
- goto fail7;
+ goto fail6;
epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
epp->ep_adv_cap_mask = els.els_adv_cap_mask;
@@ -194,11 +179,11 @@ medford2_board_cfg(
else if ((rc == ENOTSUP) || (rc == ENOENT))
encp->enc_bug61265_workaround = B_FALSE;
else
- goto fail8;
+ goto fail7;
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
- goto fail9;
+ goto fail8;
/*
* The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -210,7 +195,7 @@ medford2_board_cfg(
/* Check capabilities of running datapath firmware */
if ((rc = ef10_get_datapath_caps(enp)) != 0)
- goto fail10;
+ goto fail9;
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
@@ -218,7 +203,7 @@ medford2_board_cfg(
/* Get the RX DMA end padding alignment configuration */
if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
if (rc != EACCES)
- goto fail11;
+ goto fail10;
/* Assume largest tail padding size supported by hardware */
end_padding = 256;
@@ -270,13 +255,13 @@ medford2_board_cfg(
* can result in time-of-check/time-of-use bugs.
*/
if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
- goto fail12;
+ goto fail11;
encp->enc_privilege_mask = mask;
/* Get interrupt vector limits */
if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail13;
+ goto fail12;
/* Ignore error (cannot query vector limits from a VF). */
base = 0;
@@ -299,14 +284,12 @@ medford2_board_cfg(
rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
- goto fail14;
+ goto fail13;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
-fail14:
- EFSYS_PROBE(fail14);
fail13:
EFSYS_PROBE(fail13);
fail12:
diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c
index 352ae50..cac5d29 100644
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -46,13 +46,11 @@ medford_nic_get_required_pcie_bandwidth(
medford_board_cfg(
__in efx_nic_t *enp)
{
- efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint8_t mac_addr[6] = { 0 };
uint32_t board_type = 0;
ef10_link_state_t els;
efx_port_t *epp = &(enp->en_port);
- uint32_t port;
uint32_t pf;
uint32_t vf;
uint32_t mask;
@@ -77,20 +75,6 @@ medford_board_cfg(
EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
-
- if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
- goto fail1;
-
- /*
- * NOTE: The MCDI protocol numbers ports from zero.
- * The common code MCDI interface numbers ports from one.
- */
- emip->emi_port = port + 1;
-
- if ((rc = ef10_external_port_mapping(enp, port,
- &encp->enc_external_port)) != 0)
- goto fail2;
-
/*
* Get PCIe function number from firmware (used for
* per-function privilege and dynamic config info).
@@ -98,7 +82,7 @@ medford_board_cfg(
* - PCIe VF: pf = parent PF, vf = VF number.
*/
if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
- goto fail3;
+ goto fail1;
encp->enc_pf = pf;
encp->enc_vf = vf;
@@ -127,7 +111,7 @@ medford_board_cfg(
rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
}
if (rc != 0)
- goto fail4;
+ goto fail2;
EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
@@ -138,7 +122,7 @@ medford_board_cfg(
if (rc == EACCES)
board_type = 0;
else
- goto fail5;
+ goto fail3;
}
encp->enc_board_type = board_type;
@@ -146,11 +130,11 @@ medford_board_cfg(
/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
- goto fail6;
+ goto fail4;
/* Obtain the default PHY advertised capabilities */
if ((rc = ef10_phy_get_link(enp, &els)) != 0)
- goto fail7;
+ goto fail5;
epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
epp->ep_adv_cap_mask = els.els_adv_cap_mask;
@@ -194,11 +178,11 @@ medford_board_cfg(
else if ((rc == ENOTSUP) || (rc == ENOENT))
encp->enc_bug61265_workaround = B_FALSE;
else
- goto fail8;
+ goto fail6;
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
- goto fail9;
+ goto fail7;
/*
* The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -210,7 +194,7 @@ medford_board_cfg(
/* Check capabilities of running datapath firmware */
if ((rc = ef10_get_datapath_caps(enp)) != 0)
- goto fail10;
+ goto fail8;
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
@@ -218,7 +202,7 @@ medford_board_cfg(
/* Get the RX DMA end padding alignment configuration */
if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
if (rc != EACCES)
- goto fail11;
+ goto fail9;
/* Assume largest tail padding size supported by hardware */
end_padding = 256;
@@ -270,13 +254,13 @@ medford_board_cfg(
* can result in time-of-check/time-of-use bugs.
*/
if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
- goto fail12;
+ goto fail10;
encp->enc_privilege_mask = mask;
/* Get interrupt vector limits */
if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail13;
+ goto fail11;
/* Ignore error (cannot query vector limits from a VF). */
base = 0;
@@ -299,16 +283,12 @@ medford_board_cfg(
rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
- goto fail14;
+ goto fail12;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
-fail14:
- EFSYS_PROBE(fail14);
-fail13:
- EFSYS_PROBE(fail13);
fail12:
EFSYS_PROBE(fail12);
fail11:
--
2.7.4
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