[dpdk-dev] [PATCH v3 4/6] compress/octeontx: add ops enq deq apis

[Verma, Shally]

>-----Original Message-----
>From: De Lara Guarch, Pablo <pablo.de.lara.guarch at intel.com>
>Sent: 24 July 2018 04:11
>To: Gupta, Ashish <Ashish.Gupta at cavium.com>
>Cc: dev at dpdk.org; Athreya, Narayana Prasad <NarayanaPrasad.Athreya at cavium.com>; Challa, Mahipal
><Mahipal.Challa at cavium.com>; Verma, Shally <Shally.Verma at cavium.com>; Sahu, Sunila <Sunila.Sahu at cavium.com>
>Subject: RE: [PATCH v3 4/6] compress/octeontx: add ops enq deq apis
>
>External Email
>
>Hi Ashish,
>
>
>> -----Original Message-----
>> From: Ashish Gupta [mailto:Ashish.Gupta at caviumnetworks.com]
>> Sent: Friday, July 20, 2018 8:05 PM
>> To: De Lara Guarch, Pablo <pablo.de.lara.guarch at intel.com>
>> Cc: dev at dpdk.org; narayanaprasad.athreya at cavium.com;
>> mahipal.challa at cavium.com; Ashish Gupta
>> <ashish.gupta at caviumnetworks.com>; Shally Verma
>> <shally.verma at caviumnetworks.com>; Sunila Sahu
>> <sunila.sahu at caviumnetworks.com>
>> Subject: [PATCH v3 4/6] compress/octeontx: add ops enq deq apis
>>
>> Add enqueue/dequeue APIs to perform compression/decompression operations
>>
>> Signed-off-by: Ashish Gupta <ashish.gupta at caviumnetworks.com>
>> Signed-off-by: Shally Verma <shally.verma at caviumnetworks.com>
>> Signed-off-by: Sunila Sahu <sunila.sahu at caviumnetworks.com>
>> ---
>>  drivers/compress/octeontx/otx_zip.c     |  49 +++++++++
>>  drivers/compress/octeontx/otx_zip.h     | 169
>> ++++++++++++++++++++++++++++++++
>>  drivers/compress/octeontx/otx_zip_pmd.c | 119 ++++++++++++++++++++++
>>  3 files changed, 337 insertions(+)
>>
>
>...
>
>>  int
>>  zipvf_create(struct rte_compressdev *compressdev)  { diff --git
>> a/drivers/compress/octeontx/otx_zip.h b/drivers/compress/octeontx/otx_zip.h
>> index 3fcd86a86..73a99e624 100644
>> --- a/drivers/compress/octeontx/otx_zip.h
>> +++ b/drivers/compress/octeontx/otx_zip.h
>
>...
>
>> +
>> +static inline int
>> +zipvf_prepare_in_buf(struct zip_stream *zstrm, struct rte_comp_op *op)
>> +{
>> +     uint32_t offset, inlen;
>> +     union zip_zptr_s *sg_list = NULL;
>> +     struct rte_mbuf *m_src;
>> +     union zip_inst_s *inst = zstrm->inst;
>> +     rte_iova_t iova;
>> +
>> +     inlen = op->src.length;
>> +     offset = op->src.offset;
>> +     m_src = op->m_src;
>> +
>> +     if (m_src->nb_segs == 1) {
>> +             /* Prepare direct input data pointer */
>> +             inst->s.dg = 0;
>> +             inst->s.inp_ptr_addr.s.addr =
>> +                     rte_pktmbuf_iova_offset(m_src, offset);
>> +             inst->s.inp_ptr_ctl.s.length = inlen;
>> +             return 0;
>> +     }
>> +
>> +     ZIP_PMD_INFO("Input packet is segmented\n");
>> +
>> +     /* Packet is segmented, create gather buffer */
>
>Looks like you actually support SGL, even though you are not setting that in the capabilities.
>Now that the SGL tests are available, you should check if the PMD passes the tests
>and update the capabilities accordingly.
>
>Also, you should take into account if offset is big enough to cross boundaries
>between segments (so first segment to be compressed/decompressed is not the first segment of the SGL).
>Look at the comments that I made in the ZLIB PMD (partly based on comments left in the ISAL PMD),
>since they should apply to this case too.
Ok. Will take care when we add SGL support. Right now, we're planning to make 1st release with Linear buffer support only.

Thanks
Shally
>
>> +     inst->s.dg = 1;
>> +     iova = rte_mempool_virt2iova(zstrm->bufs[IN_DATA_BUF]);
>> +     if (iova & 0xF) {
>> +             /* Align it to 16 Byte address */
>> +             iova = ZIP_ALIGN_ROUNDUP(iova, ZIP_SGPTR_ALIGN);
>> +     }
>> +
>>