[dpdk-dev] [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare exchange

Jerin Jacob Kollanukkaran jerinj at marvell.com
Wed Aug 14 14:40:02 CEST 2019


> -----Original Message-----
> From: Phil Yang (Arm Technology China) <Phil.Yang at arm.com>
> Sent: Wednesday, August 14, 2019 3:55 PM
> To: Jerin Jacob Kollanukkaran <jerinj at marvell.com>; thomas at monjalon.net;
> gage.eads at intel.com; dev at dpdk.org
> Cc: hemant.agrawal at nxp.com; Honnappa Nagarahalli
> <Honnappa.Nagarahalli at arm.com>; Gavin Hu (Arm Technology China)
> <Gavin.Hu at arm.com>; nd <nd at arm.com>; nd <nd at arm.com>
> Subject: [EXT] RE: [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare
> exchange
> 
> External Email
> 
> ----------------------------------------------------------------------
> > -----Original Message-----
> > From: Jerin Jacob Kollanukkaran <jerinj at marvell.com>
> > Sent: Wednesday, August 14, 2019 4:46 PM
> > To: Phil Yang (Arm Technology China) <Phil.Yang at arm.com>;
> > thomas at monjalon.net; gage.eads at intel.com; dev at dpdk.org
> > Cc: hemant.agrawal at nxp.com; Honnappa Nagarahalli
> > <Honnappa.Nagarahalli at arm.com>; Gavin Hu (Arm Technology China)
> > <Gavin.Hu at arm.com>; nd <nd at arm.com>
> > Subject: RE: [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare
> > exchange
> >
> > > -----Original Message-----
> > > From: Phil Yang <phil.yang at arm.com>
> > > Sent: Wednesday, August 14, 2019 1:58 PM
> > > To: thomas at monjalon.net; Jerin Jacob Kollanukkaran
> > <jerinj at marvell.com>;
> > > gage.eads at intel.com; dev at dpdk.org
> > > Cc: hemant.agrawal at nxp.com; Honnappa.Nagarahalli at arm.com;
> > > gavin.hu at arm.com; nd at arm.com
> > > Subject: [EXT] [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare
> > > exchange
> > > +#define __HAS_ACQ(mo) ((mo) != __ATOMIC_RELAXED && (mo) !=
> > > +__ATOMIC_RELEASE) #define __HAS_RLS(mo) ((mo) ==
> > > __ATOMIC_RELEASE || (mo) == __ATOMIC_ACQ_REL || \
> > > +					  (mo) == __ATOMIC_SEQ_CST)
> > > +
> > > +#define __MO_LOAD(mo)  (__HAS_ACQ((mo)) ? __ATOMIC_ACQUIRE :
> > > +__ATOMIC_RELAXED) #define __MO_STORE(mo) (__HAS_RLS((mo)) ?
> > > +__ATOMIC_RELEASE : __ATOMIC_RELAXED)
> > > +
> > > +#if defined(__ARM_FEATURE_ATOMICS) ||
> > > defined(RTE_ARM_FEATURE_ATOMICS)
> > > +#define __ATOMIC128_CAS_OP(cas_op_name, op_string)
> \
> > > +static __rte_noinline rte_int128_t                                          \
> >
> >
> > Could you check the cost of making it as __rte_noinline?
> > If it is costly, How about having two versions, one with
> > __rte_noinline to make compliance with arm64 procedure call standard
> > for old gcc and clang.
> > Other one without explicit register hardcoding + inline for latest gcc
> 
> Hi Jerin,

Hi Phil Yang,

> According to the stack_lf_perf_autotest, making it as __rte_noinline has no
> overhead on ThunderX2 with GCC 8.3.
> The 'Average cycles per object push/pop' numbers for __rte_noinline and
> __rte_always_inline versions are nearly the same.

I tested with octeontx2 as well. It is yielding similar result. 
No change is expected in this patch then.



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