[dpdk-dev] [PATCH 11/11] doc: add documentation for OCTEON TX2 crypto PMD
Anoob Joseph
anoobj at marvell.com
Fri Aug 30 08:28:21 CEST 2019
Adding feature list and user guide for OCTEONTX2 crypto PMD.
Signed-off-by: Ankur Dwivedi <adwivedi at marvell.com>
Signed-off-by: Anoob Joseph <anoobj at marvell.com>
---
MAINTAINERS | 7 ++
doc/guides/cryptodevs/features/octeontx2.ini | 62 ++++++++++++
doc/guides/cryptodevs/index.rst | 1 +
doc/guides/cryptodevs/octeontx2.rst | 142 +++++++++++++++++++++++++++
doc/guides/platform/octeontx2.rst | 3 +
5 files changed, 215 insertions(+)
create mode 100644 doc/guides/cryptodevs/features/octeontx2.ini
create mode 100644 doc/guides/cryptodevs/octeontx2.rst
diff --git a/MAINTAINERS b/MAINTAINERS
index 4100260..eef64f7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -965,6 +965,13 @@ F: drivers/crypto/mvsam/
F: doc/guides/cryptodevs/mvsam.rst
F: doc/guides/cryptodevs/features/mvsam.ini
+Marvell OCTEON TX2 crypto
+M: Ankur Dwivedi <adwivedi at marvell.com>
+M: Anoob Joseph <anoobj at marvell.com>
+F: drivers/crypto/octeontx2/
+F: doc/guides/cryptodevs/octeontx2.rst
+F: doc/guides/cryptodevs/features/octeontx2.ini
+
Null Crypto
M: Declan Doherty <declan.doherty at intel.com>
F: drivers/crypto/null/
diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini
new file mode 100644
index 0000000..ac76b11
--- /dev/null
+++ b/doc/guides/cryptodevs/features/octeontx2.ini
@@ -0,0 +1,62 @@
+;
+; Supported features of the 'octeontx2' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+HW Accelerated = Y
+In Place SGL = Y
+OOP SGL In LB Out = Y
+OOP SGL In SGL Out = Y
+
+;
+; Supported crypto algorithms of 'octeontx2' crypto driver.
+;
+[Cipher]
+NULL = Y
+3DES CBC = Y
+3DES ECB = Y
+AES CBC (128) = Y
+AES CBC (192) = Y
+AES CBC (256) = Y
+AES CTR (128) = Y
+AES CTR (192) = Y
+AES CTR (256) = Y
+AES XTS (128) = Y
+AES XTS (256) = Y
+DES CBC = Y
+KASUMI F8 = Y
+SNOW3G UEA2 = Y
+ZUC EEA3 = Y
+
+;
+; Supported authentication algorithms of 'octeontx2' crypto driver.
+;
+[Auth]
+NULL = Y
+AES GMAC = Y
+KASUMI F9 = Y
+MD5 = Y
+MD5 HMAC = Y
+SHA1 = Y
+SHA1 HMAC = Y
+SHA224 = Y
+SHA224 HMAC = Y
+SHA256 = Y
+SHA256 HMAC = Y
+SHA384 = Y
+SHA384 HMAC = Y
+SHA512 = Y
+SHA512 HMAC = Y
+SNOW3G UIA2 = Y
+ZUC EIA3 = Y
+
+;
+; Supported AEAD algorithms of 'octeontx2' crypto driver.
+;
+[AEAD]
+AES GCM (128) = Y
+AES GCM (192) = Y
+AES GCM (256) = Y
diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst
index 83610e6..1efb3fa 100644
--- a/doc/guides/cryptodevs/index.rst
+++ b/doc/guides/cryptodevs/index.rst
@@ -19,6 +19,7 @@ Crypto Device Drivers
dpaa_sec
kasumi
octeontx
+ octeontx2
openssl
mvsam
null
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
new file mode 100644
index 0000000..a2cbb50
--- /dev/null
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -0,0 +1,142 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2019 Marvell International Ltd.
+
+
+Marvell OCTEON TX2 Crypto Poll Mode Driver
+==========================================
+
+The OCTEON TX2 crypto poll mode driver provides support for offloading
+cryptographic operations to cryptographic accelerator units on the
+**OCTEON TX2** :sup:`®` family of processors (CN9XXX).
+
+More information about OCTEON TX2 SoCs may be obtained from `<https://www.marvell.com>`_
+
+Features
+--------
+
+The OCTEON TX2 crypto PMD has support for:
+
+Cipher algorithms:
+
+* ``RTE_CRYPTO_CIPHER_NULL``
+* ``RTE_CRYPTO_CIPHER_3DES_CBC``
+* ``RTE_CRYPTO_CIPHER_3DES_ECB``
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES_CTR``
+* ``RTE_CRYPTO_CIPHER_AES_XTS``
+* ``RTE_CRYPTO_CIPHER_DES_CBC``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
+
+Hash algorithms:
+
+* ``RTE_CRYPTO_AUTH_NULL``
+* ``RTE_CRYPTO_AUTH_AES_GMAC``
+* ``RTE_CRYPTO_AUTH_KASUMI_F9``
+* ``RTE_CRYPTO_AUTH_MD5``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA1``
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA512``
+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
+* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
+
+AEAD algorithms:
+
+* ``RTE_CRYPTO_AEAD_AES_GCM``
+
+
+Installation
+------------
+
+The OCTEON TX2 crypto PMD may be compiled natively on an OCTEON TX2 platform or
+cross-compiled on an x86 platform.
+
+Enable OCTEON TX2 crypto PMD in your config file:
+
+* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y``
+
+Refer to :doc:`../platform/octeontx2` for instructions to build your DPDK
+application.
+
+.. note::
+
+ The OCTEON TX2 crypto PMD uses services from the kernel mode OCTEON TX2
+ crypto PF driver in linux. This driver is included in the OCTEON TX SDK.
+
+Initialization
+--------------
+
+List the CPT PF devices available on your OCTEON TX2 platform:
+
+.. code-block:: console
+
+ lspci -d:a0fd
+
+``a0fd`` is the CPT PF device id. You should see output similar to:
+
+.. code-block:: console
+
+ 0002:10:00.0 Class 1080: Device 177d:a0fd
+
+Set ``sriov_numvfs`` on the CPT PF device, to create a VF:
+
+.. code-block:: console
+
+ echo 1 > /sys/bus/pci/drivers/octeontx2-cpt/0002:10:00.0/sriov_numvfs
+
+Bind the CPT VF device to the vfio_pci driver:
+
+.. code-block:: console
+
+ echo '177d a0fe' > /sys/bus/pci/drivers/vfio-pci/new_id
+ echo 0002:10:00.1 > /sys/bus/pci/devices/0002:10:00.1/driver/unbind
+ echo 0002:10:00.1 > /sys/bus/pci/drivers/vfio-pci/bind
+
+Another way to bind the VF would be to use the ``dpdk-devbind.py`` script:
+
+.. code-block:: console
+
+ cd <dpdk directory>
+ ./usertools/dpdk-devbind.py -u 0002:10:00.1
+ ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1
+
+.. note::
+
+ Ensure that sufficient huge pages are available for your application::
+
+ echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
+
+ Refer to :ref:`linux_gsg_hugepages` for more details.
+
+Debugging Options
+-----------------
+
+.. _table_octeontx2_crypto_debug_options:
+
+.. table:: OCTEON TX2 crypto PMD debug options
+
+ +---+------------+-------------------------------------------------------+
+ | # | Component | EAL log command |
+ +===+============+=======================================================+
+ | 1 | CPT | --log-level='pmd\.crypto\.octeontx2,8' |
+ +---+------------+-------------------------------------------------------+
+
+Testing
+-------
+
+The symmetric crypto operations on OCTEON TX2 crypto PMD may be verified by running the test
+application:
+
+.. code-block:: console
+
+ ./test
+ RTE>>cryptodev_octeontx2_autotest
diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 4194a43..f06dc68 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -132,6 +132,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
#. **DMA Rawdev Driver**
See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.
+#. **Crypto Device Driver**
+ See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
+
Procedure to Setup Platform
---------------------------
--
2.7.4
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