[dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific flags
Thomas Monjalon
thomas at monjalon.net
Mon Jan 14 12:32:28 CET 2019
09/01/2019 11:39, Pavan Nikhilesh Bhagavatula:
> From: Pavan Nikhilesh <pbhagavatula at marvell.com>
>
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE.
> Add support to set micro arch specific flags.
>
> Signed-off-by: Jerin Jacob <jerinj at marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula at marvell.com>
> ---
> flags_cavium = [
> - ['RTE_MACHINE', '"thunderx"'],
> ['RTE_CACHE_LINE_SIZE', 128],
> ['RTE_MAX_NUMA_NODES', 2],
> ['RTE_MAX_LCORE', 96],
> - ['RTE_MAX_VFIO_GROUPS', 128],
> - ['RTE_USE_C11_MEM_MODEL', false]]
> + ['RTE_MAX_VFIO_GROUPS', 128]]
[...]
> +flags_thunderx_extra = [
> + ['RTE_MACHINE', '"thunderx"'],
> + ['RTE_USE_C11_MEM_MODEL', false]]
[..]
> +machine_args_cavium = [
> + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> + ['native', ['-march=native']],
> + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
This patch is not only adding infra, it also change some Cavium config.
What about splitting, and explaining the change of RTE_USE_C11_MEM_MODEL?
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