[dpdk-dev] [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER
shahafs at mellanox.com
Sun Mar 24 07:37:42 CET 2019
Pradeep Satyanarayana wrote on Saturday, March 23, 2019 12:58 AM
>Thomas Monjalon <thomas at monjalon.net> wrote on 03/22/2019 10:51:17 AM:
>> Date: 03/22/2019 10:51 AM
>> Subject: Re: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER
>> 22/03/2019 16:30, Pradeep Satyanarayana:
>> > Thomas Monjalon <thomas at monjalon.net> wrote on 03/22/2019 01:49:03 AM:
>> > > 22/03/2019 02:40, Pradeep Satyanarayana:
>> > > > - rte_[rw]mb (general memory barrier) --> should be lwsync
>> > >
>> > > This is what may be discussed.
>> > > The assumption is that the general memory barrier should cover
>> > > all cases (CPU caches, SMP and I/O).
>> > > That's why we think it should "sync" for Power.
>> > In that case, at a minimum we must de-link rte_smp_[rw]mb from rte_[rw]mb
>> > and retain it as lwsync. Agreed?
>> I have no clue about what is needed for SMP barrier in Power.
>> As long as it works as expected, no problem.
>We will try that out and report back here, later next week
Till then, i think there are 2 orthogonal issues:
1. ppc rte_wmb is incorrect
2. ppc rte_smp_[rw]mb may be improved.
for #1 the current patch from Dekel seems to be OK. do you agree?
for #2 i guess you will check and come back w/ patch/answer?
More information about the dev