[dpdk-dev] [PATCH] librte_eal: fix mcslock hang on weak memory

Thomas Monjalon thomas at monjalon.net
Tue Oct 6 23:49:45 CEST 2020


31/08/2020 20:45, Honnappa Nagarahalli:
> 
> Hi Diogo,
> 
> Thanks for your explanation.
> 
> As documented in https://developer.arm.com/documentation/ddi0487/fc  B2.9.5 Load-Exclusive and Store-Exclusive instruction usage restrictions:
> " Between the Load-Exclusive and the Store-Exclusive, there are no explicit memory accesses, preloads, 
> direct or indirect System register writes, address translation instructions, cache or TLB maintenance
> instructions, exception generating instructions, exception returns, or indirect branches."
> [Honnappa] This is a requirement on the software, not on the micro-architecture.
> We are having few discussions internally, will get back soon.
> 
> So it is not allowed to insert (1) & (4) between (2, 3). The cmpxchg operation is atomic.


Please what is the conclusion?





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