[PATCH] net/mlx5: fix GENEVE resource management

[Raslan Darawsheh]

Hi,

> -----Original Message-----
> From: Suanming Mou <suanmingm at nvidia.com>
> Sent: Wednesday, November 16, 2022 11:37 AM
> To: Matan Azrad <matan at nvidia.com>; Slava Ovsiienko
> <viacheslavo at nvidia.com>
> Cc: dev at dpdk.org; Raslan Darawsheh <rasland at nvidia.com>
> Subject: [PATCH] net/mlx5: fix GENEVE resource management
> 
> The item translation split causes GENEVE TLV option resource register
> function flow_dev_geneve_tlv_option_resource_register() to be called
> twice incorrectly both in spec and mask translation.
> 
> In SWS mode the refcnt will only be decreased by 1 in flow release.
> The refcnt will never be 0 again, it causes the resource be leaked.
> In HWS mode the resource is allocated as global, the refcnt should
> not be increased after the resource be allocated. And the resource
> should be released during PMD exists.
> 
> This commit fixes GENEVE resource management.
> 
> Fixes: 75a00812b18f ("net/mlx5: add hardware steering item translation")
> Fixes: cd4ab742064a ("net/mlx5: split flow item matcher and value
> translation")
> 
> Signed-off-by: Suanming Mou <suanmingm at nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo at nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh