[PATCH 3/9] common/cnxk: configure fc hist bits

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar at marvell.com>

New parameter added inside SQ structure to control the fc_hyst_bits.
Instead of count on all updates each SQ can tune his own hysteresis
level.

Signed-off-by: Satha Rao <skoteshwar at marvell.com>
---
 drivers/common/cnxk/roc_nix.h       | 1 +
 drivers/common/cnxk/roc_nix_queue.c | 5 ++---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 47ee078c2e..96756b1a2b 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -354,6 +354,7 @@ struct roc_nix_sq {
 	uint16_t cq_drop_thresh;
 	bool sso_ena;
 	bool cq_ena;
+	uint8_t fc_hyst_bits;
 	/* End of Input parameters */
 	uint16_t sqes_per_sqb_log2;
 	struct roc_nix *roc_nix;
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 385f1ba04e..287a489e7f 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -1025,9 +1025,8 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
 	else
 		aura.fc_stype = 0x3; /* STSTP */
 	aura.fc_addr = (uint64_t)sq->fc;
-	aura.fc_hyst_bits = 1; /* Store count on all updates */
-	rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura,
-				 &pool, 0);
+	aura.fc_hyst_bits = sq->fc_hyst_bits & 0xF;
+	rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0);
 	if (rc)
 		goto fail;
 
-- 
2.25.1