[PATCH v3 2/7] common/mlx5: reorder modification field PRM list
    Michael Baum 
    michaelba at nvidia.com
       
    Mon Feb 26 14:45:51 CET 2024
    
    
  
Reorder modification field PRM list according to values from lowest to
highest.
This patch also removes value specification from all fields which their
value is one more than previous one.
Signed-off-by: Michael Baum <michaelba at nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski at nvidia.com>
---
 drivers/common/mlx5/mlx5_prm.h | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 6a8cb7a8aa..6967acbdc3 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -816,6 +816,7 @@ enum mlx5_modification_field {
 	MLX5_MODI_OUT_IPV6_HOPLIMIT,
 	MLX5_MODI_IN_IPV6_HOPLIMIT,
 	MLX5_MODI_META_DATA_REG_A,
+	MLX5_MODI_OUT_IP_PROTOCOL,
 	MLX5_MODI_META_DATA_REG_B = 0x50,
 	MLX5_MODI_META_REG_C_0,
 	MLX5_MODI_META_REG_C_1,
@@ -829,32 +830,31 @@ enum mlx5_modification_field {
 	MLX5_MODI_IN_TCP_SEQ_NUM,
 	MLX5_MODI_OUT_TCP_ACK_NUM,
 	MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
+	MLX5_MODI_OUT_ESP_SPI = 0x5E,
 	MLX5_MODI_GTP_TEID = 0x6E,
 	MLX5_MODI_OUT_IP_ECN = 0x73,
 	MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75,
-	MLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76,
+	MLX5_MODI_GTPU_FIRST_EXT_DW_0,
 	MLX5_MODI_HASH_RESULT = 0x81,
+	MLX5_MODI_OUT_ESP_SEQ_NUM,
 	MLX5_MODI_IN_MPLS_LABEL_0 = 0x8a,
 	MLX5_MODI_IN_MPLS_LABEL_1,
 	MLX5_MODI_IN_MPLS_LABEL_2,
 	MLX5_MODI_IN_MPLS_LABEL_3,
 	MLX5_MODI_IN_MPLS_LABEL_4,
-	MLX5_MODI_OUT_IP_PROTOCOL = 0x4A,
-	MLX5_MODI_META_REG_C_8 = 0x8F,
-	MLX5_MODI_META_REG_C_9 = 0x90,
-	MLX5_MODI_META_REG_C_10 = 0x91,
-	MLX5_MODI_META_REG_C_11 = 0x92,
-	MLX5_MODI_META_REG_C_12 = 0x93,
-	MLX5_MODI_META_REG_C_13 = 0x94,
-	MLX5_MODI_META_REG_C_14 = 0x95,
-	MLX5_MODI_META_REG_C_15 = 0x96,
+	MLX5_MODI_META_REG_C_8,
+	MLX5_MODI_META_REG_C_9,
+	MLX5_MODI_META_REG_C_10,
+	MLX5_MODI_META_REG_C_11,
+	MLX5_MODI_META_REG_C_12,
+	MLX5_MODI_META_REG_C_13,
+	MLX5_MODI_META_REG_C_14,
+	MLX5_MODI_META_REG_C_15,
 	MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS = 0x11C,
-	MLX5_MODI_OUT_IPV4_TOTAL_LEN = 0x11D,
-	MLX5_MODI_OUT_IPV6_PAYLOAD_LEN = 0x11E,
-	MLX5_MODI_OUT_IPV4_IHL = 0x11F,
-	MLX5_MODI_OUT_TCP_DATA_OFFSET = 0x120,
-	MLX5_MODI_OUT_ESP_SPI = 0x5E,
-	MLX5_MODI_OUT_ESP_SEQ_NUM = 0x82,
+	MLX5_MODI_OUT_IPV4_TOTAL_LEN,
+	MLX5_MODI_OUT_IPV6_PAYLOAD_LEN,
+	MLX5_MODI_OUT_IPV4_IHL,
+	MLX5_MODI_OUT_TCP_DATA_OFFSET,
 	MLX5_MODI_OUT_IPSEC_NEXT_HDR = 0x126,
 	MLX5_MODI_INVALID = INT_MAX,
 };
-- 
2.25.1
    
    
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