[PATCH v2 09/15] net/txgbe: add TX head Write-Back mode for Amber-Lite NICs

[Jiawen Wu]

> diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
> index 8005283a26..5692883f60 100644
> --- a/drivers/net/txgbe/base/txgbe_type.h
> +++ b/drivers/net/txgbe/base/txgbe_type.h
> @@ -723,6 +723,8 @@ struct txgbe_phy_info {
>  #define TXGBE_DEVARG_FFE_MAIN		"ffe_main"
>  #define TXGBE_DEVARG_FFE_PRE		"ffe_pre"
>  #define TXGBE_DEVARG_FFE_POST		"ffe_post"
> +#define TXGBE_DEVARG_TX_HEAD_WB		"tx_headwb"
> +#define TXGBE_DEVARG_TX_HEAD_WB_SIZE	"tx_headwb_size"
> 
>  static const char * const txgbe_valid_arguments[] = {
>  	TXGBE_DEVARG_BP_AUTO,
> @@ -733,6 +735,8 @@ static const char * const txgbe_valid_arguments[] = {
>  	TXGBE_DEVARG_FFE_MAIN,
>  	TXGBE_DEVARG_FFE_PRE,
>  	TXGBE_DEVARG_FFE_POST,
> +	TXGBE_DEVARG_TX_HEAD_WB,
> +	TXGBE_DEVARG_TX_HEAD_WB_SIZE,
>  	NULL
>  };
> 
> @@ -783,6 +787,8 @@ struct txgbe_devargs {
>  	u16 poll;
>  	u16 present;
>  	u16 sgmii;
> +	u16 tx_headwb;
> +	u16 tx_headwb_size;
>  };
> 
>  struct txgbe_hw {
> diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
> index a854b40b9f..ed84594105 100644
> --- a/drivers/net/txgbe/txgbe_ethdev.c
> +++ b/drivers/net/txgbe/txgbe_ethdev.c
> @@ -513,6 +513,9 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
>  	u16 ffe_main = 27;
>  	u16 ffe_pre = 8;
>  	u16 ffe_post = 44;
> +	/* New devargs for amberlite config */
> +	u16 tx_headwb = 1;
> +	u16 tx_headwb_size = 16;
> 
>  	if (devargs == NULL)
>  		goto null;
> @@ -537,6 +540,10 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
>  			   &txgbe_handle_devarg, &ffe_pre);
>  	rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST,
>  			   &txgbe_handle_devarg, &ffe_post);
> +	rte_kvargs_process(kvlist, TXGBE_DEVARG_TX_HEAD_WB,
> +			   &txgbe_handle_devarg, &tx_headwb);
> +	rte_kvargs_process(kvlist, TXGBE_DEVARG_TX_HEAD_WB_SIZE,
> +			   &txgbe_handle_devarg, &tx_headwb_size);
>  	rte_kvargs_free(kvlist);
> 
>  null:
> @@ -544,6 +551,8 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
>  	hw->devarg.poll = poll;
>  	hw->devarg.present = present;
>  	hw->devarg.sgmii = sgmii;
> +	hw->devarg.tx_headwb = tx_headwb;
> +	hw->devarg.tx_headwb_size = tx_headwb_size;
>  	hw->phy.ffe_set = ffe_set;
>  	hw->phy.ffe_main = ffe_main;
>  	hw->phy.ffe_pre = ffe_pre;

Add the strings into RTE_PMD_REGISTER_PARAM_STRING().

> diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c
> index 558ffbf73f..9846ce3c56 100644
> --- a/drivers/net/txgbe/txgbe_rxtx.c
> +++ b/drivers/net/txgbe/txgbe_rxtx.c
> @@ -92,14 +92,29 @@ txgbe_tx_free_bufs(struct txgbe_tx_queue *txq)
>  	int i, nb_free = 0;
>  	struct rte_mbuf *m, *free[RTE_TXGBE_TX_MAX_FREE_BUF_SZ];
> 
> -	/* check DD bit on threshold descriptor */
> -	status = txq->tx_ring[txq->tx_next_dd].dw3;
> -	if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) {
> -		if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
> -			txgbe_set32_masked(txq->tdc_reg_addr,
> -				TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH);
> -		return 0;
> -	}
> +	if (txq->headwb_mem) {
> +		uint16_t tx_last_dd = txq->nb_tx_desc +
> +				      txq->tx_next_dd - txq->tx_free_thresh;
> +		if (tx_last_dd >= txq->nb_tx_desc)
> +			tx_last_dd -= txq->nb_tx_desc;
> +
> +		volatile uint16_t head = (uint16_t)*(txq->headwb_mem);
> +
> +		if (txq->tx_next_dd > head && head > tx_last_dd)
> +			return 0;
> +		else if (tx_last_dd > txq->tx_next_dd &&
> +				(head > tx_last_dd || head < txq->tx_next_dd))
> +			return 0;
> +	} else {
> +		/* check DD bit on threshold descriptor */
> +		status = txq->tx_ring[txq->tx_next_dd].dw3;
> +		if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) {
> +			if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
> +				txgbe_set32_masked(txq->tdc_reg_addr,
> +					TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH);
> +			return 0;
> +		}
> +}

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