[PATCH v5 32/34] net/intel: support wider x86 vectors for Rx rearm

[Burakov, Anatoly]

On 6/9/2025 1:54 PM, Bruce Richardson wrote:
> On Fri, Jun 06, 2025 at 06:17:07PM +0100, Anatoly Burakov wrote:
>> Currently, for 32-byte descriptor format, only SSE instruction set is
>> supported. Add implementation for AVX2 and AVX512 instruction sets. Since
>> we are using Rx descriptor definitions from common code, we can just use
>> the generic descriptor definition, as we only ever write the first 16 bytes
>> of it, and the layout is always the same for that part.
>>
>> Signed-off-by: Anatoly Burakov <anatoly.burakov at intel.com>
>> ---
> 
> Acked-by: Bruce Richardson <bruce.richardson at intel.com>
> 
> Two small comments inline below.
> 

<snip>

>> -#ifdef RTE_NET_INTEL_USE_16BYTE_DESC
>>   #ifdef __AVX2__
>> -/* AVX2 version for 16-byte descriptors, handles 4 buffers at a time */
>> -static __rte_always_inline void
>> -_ci_rxq_rearm_avx2(struct ci_rx_queue *rxq)
>> +/**
>> + * Reformat data from mbuf to descriptor for one RX descriptor, using AVX2 instruction set.
>> + *
>> + * Note that for 32-byte descriptors, the second parameter must be zeroed out.
> 
> Don't need this note any more, since this function is not used for 32-byte
> descriptors.

Well, technically the note is still true - if you want to use this 
function with 32-byte descriptors, you will have to do what the note 
says. We don't *do* it, but that bears no effect on the properties of 
the function itself.

-- 
Thanks,
Anatoly