[PATCH 4/6] common/cnxk: update inbound CPT LF ID

[Rahul Bhansali]

Inbound CPT LF ID update for Rx inline config.

Signed-off-by: Rahul Bhansali <rbhansali at marvell.com>
---
 drivers/common/cnxk/roc_nix_inl.c      | 10 +++++++++-
 drivers/common/cnxk/roc_nix_inl_dev.c  |  4 +---
 drivers/common/cnxk/roc_nix_inl_priv.h |  2 +-
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 7e47151eee..bee8e25c7c 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -495,7 +495,7 @@ nix_inl_inb_ipsec_sa_tbl_setup(struct roc_nix *roc_nix)
 			if (!inl_dev->nb_inb_cptlfs)
 				def_cptq = 0;
 			else
-				def_cptq = inl_dev->nix_inb_qids[0];
+				def_cptq = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id];
 		}
 
 		res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
@@ -1997,6 +1997,14 @@ roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable)
 
 		inl_dev = idev->nix_inl_dev;
 
+		if (!roc_model_is_cn10k()) {
+			if (inl_rq->spb_ena) {
+				rc = -EINVAL;
+				plt_err("inline RQ enable is not supported rc=%d", rc);
+				return rc;
+			}
+		}
+
 		rc = nix_rq_ena_dis(&inl_dev->dev, inl_rq, enable);
 		if (rc)
 			return rc;
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 1f071df8ea..75d03c1077 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -385,7 +385,6 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
 			goto exit;
 		}
 
-		/*TODO default cptq */
 		if (!inl_dev->nb_inb_cptlfs)
 			def_cptq = 0;
 		else
@@ -646,11 +645,10 @@ nix_inl_nix_profile_config(struct nix_inl_dev *inl_dev, uint8_t profile_id)
 	sa_w = plt_log2_u32(max_sa);
 	sa_pow2_sz = plt_log2_u32(inb_sa_sz);
 
-	/*TODO default cptq, Assuming Reassembly cpt lf ID at inl_dev->inb_cpt_lf_id + 1 */
 	if (!inl_dev->nb_inb_cptlfs)
 		def_cptq = 0;
 	else
-		def_cptq = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id + 1];
+		def_cptq = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id];
 
 	res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
 	if (res_addr_offset)
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index 33073b2f34..5c12fb1160 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -134,7 +134,7 @@ struct nix_inl_dev {
 
 #define NIX_INL_REASS_GEN_CFG                                                                      \
 	(BIT_ULL(51) | (ROC_CPT_DFLT_ENG_GRP_SE << 48) |                                           \
-	 (ROC_IE_OW_MAJOR_OP_PROCESS_INBOUND_REASS << 32))
+	 (ROC_IE_OW_MAJOR_OP_PROCESS_INBOUND_REASS << 32 | ROC_IE_OW_INPLACE_BIT << 32))
 
 int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev);
 void nix_inl_sso_unregister_irqs(struct nix_inl_dev *inl_dev);
-- 
2.25.1