[PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API

[Bing Zhao]

Hi,

> -----Original Message-----
> From: Minggang(Gavin) Li <gavinl at nvidia.com>
> Sent: Tuesday, September 30, 2025 3:28 PM
> To: Matan Azrad <matan at nvidia.com>; Slava Ovsiienko
> <viacheslavo at nvidia.com>; Ori Kam <orika at nvidia.com>; NBU-Contact-Thomas
> Monjalon (EXTERNAL) <thomas at monjalon.net>; Dariusz Sosnowski
> <dsosnowski at nvidia.com>; Bing Zhao <bingz at nvidia.com>; Suanming Mou
> <suanmingm at nvidia.com>; Minggang(Gavin) Li <gavinl at nvidia.com>
> Cc: dev at dpdk.org; Raslan Darawsheh <rasland at nvidia.com>; stable at dpdk.org
> Subject: [PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API
> 
> The RTE action process in the HWS non-template API differs from the
> process in SWS. The bit shift handling for IPv6 DSCP was not handled in
> HWS, resulting in incorrect data in the field.
> 
> To resolve this, bit shift handling should be added to HWS.
> 
> Fixes: ec1e7a5ceb69 ("net/mlx5: update IPv6 traffic class modification")
> Cc: stable at dpdk.org
> Signed-off-by: Gavin Li <gavinl at nvidia.com>
> ---
>  drivers/net/mlx5/mlx5_flow.h    | 5 +++++
>  drivers/net/mlx5/mlx5_flow_dv.c | 6 ------
> drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++
>  3 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
> index ff61706054..6ec853f018 100644
> --- a/drivers/net/mlx5/mlx5_flow.h
> +++ b/drivers/net/mlx5/mlx5_flow.h
> @@ -3680,6 +3680,11 @@ void
>  mlx5_indirect_list_handles_release(struct rte_eth_dev *dev);
> 
>  bool mlx5_flow_is_steering_disabled(void);
> +static inline bool
> +mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv) {
> +	return priv->sh->phdev->config.ipv6_tc_fallback ==
> MLX5_IPV6_TC_OK; }
> 
>  #ifdef HAVE_MLX5_HWS_SUPPORT
> 
> diff --git a/drivers/net/mlx5/mlx5_flow_dv.c
> b/drivers/net/mlx5/mlx5_flow_dv.c index bcce1597e2..517a5e530d 100644
> --- a/drivers/net/mlx5/mlx5_flow_dv.c
> +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> @@ -1638,12 +1638,6 @@ mlx5_modify_flex_item(const struct rte_eth_dev
> *dev,
>  	}
>  }
> 
> -static inline bool
> -mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv) -{
> -	return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK;
> -}
> -
>  void
>  mlx5_flow_field_id_to_modify_info
>  		(const struct rte_flow_field_data *data, diff --git
> a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index
> 9a0aa1827e..628a47f2ce 100644
> --- a/drivers/net/mlx5/mlx5_flow_hw.c
> +++ b/drivers/net/mlx5/mlx5_flow_hw.c
> @@ -1613,6 +1613,11 @@ flow_hw_modify_field_compile(struct rte_eth_dev
> *dev,
>  			value = *(const uint8_t *)item.spec << 24;
>  			value = rte_cpu_to_be_32(value);
>  			item.spec = &value;
> +		} else if (conf->dst.field == RTE_FLOW_FIELD_IPV6_DSCP &&
> +			   !(mask[0] & MLX5_IPV6_HDR_ECN_MASK) &&
> +			   mlx5_dv_modify_ipv6_traffic_class_supported(dev-
> >data->dev_private)) {
> +			value = *(const unaligned_uint32_t *)item.spec <<
> MLX5_IPV6_HDR_DSCP_SHIFT;
> +			item.spec = &value;
>  		}
>  	} else {
>  		type = conf->operation == RTE_FLOW_MODIFY_SET ?
> --
> 2.34.1


Maybe the title can be changed to non-template API directly instead of NT HWS?

Acked-by: Bing Zhao <bingz at nvidia.com>