[PATCH v2] net/mlx5: remove counter alignment

[Rongwei Liu]

The memory footprint was increased due to the alignment.

Fixes: 820ca7361bb7fa4 ("net/mlx5: fix flow aging race condition")
Cc: rongweil at nvidia.com

Signed-off-by: Rongwei Liu <rongweil at nvidia.com>
---
 drivers/net/mlx5/mlx5_hws_cnt.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_hws_cnt.h b/drivers/net/mlx5/mlx5_hws_cnt.h
index f5b7e8f643..8d7a9d34df 100644
--- a/drivers/net/mlx5/mlx5_hws_cnt.h
+++ b/drivers/net/mlx5/mlx5_hws_cnt.h
@@ -43,7 +43,7 @@ struct mlx5_hws_cnt_dcs_mng {
 };
 
 union mlx5_hws_cnt_state {
-	alignas(RTE_CACHE_LINE_SIZE) RTE_ATOMIC(uint32_t)data;
+	RTE_ATOMIC(uint32_t) data;
 	struct {
 		uint32_t in_used:1;
 		/* Indicator whether this counter in used or in pool. */
@@ -64,7 +64,7 @@ struct mlx5_hws_cnt {
 	struct flow_counter_stats reset;
 	union mlx5_hws_cnt_state cnt_state;
 	/* This struct is only meaningful when user own this counter. */
-	alignas(RTE_CACHE_LINE_SIZE) RTE_ATOMIC(uint32_t)query_gen_when_free;
+	RTE_ATOMIC(uint32_t) query_gen_when_free;
 	/*
 	 * When PMD own this counter (user put back counter to PMD
 	 * counter pool, i.e), this field recorded value of counter
-- 
2.27.0