[PATCH 0/2] align crypto CPTR as per platform

[Akhil Goyal]

> -----Original Message-----
> From: Tejasree Kondoj <ktejasree at marvell.com>
> Sent: Monday, January 12, 2026 5:53 PM
> To: Akhil Goyal <gakhil at marvell.com>
> Cc: Anoob Joseph <anoobj at marvell.com>; Nithinsen Kaithakadan
> <nkaithakadan at marvell.com>; dev at dpdk.org
> Subject: [PATCH 0/2] align crypto CPTR as per platform
> 
> Aligning CPTR as per HW requirements for
> cnxk crypto PMD.
> 
> Nithinsen Kaithakadan (1):
>   common/cnxk: set CPT cache line size per platform
> 
> Tejasree Kondoj (1):
>   crypto/cnxk: align TLS CPTR to 256B
> 
>  drivers/common/cnxk/roc_cpt.c       |  4 +--
>  drivers/common/cnxk/roc_cpt.h       |  5 +++
>  drivers/crypto/cnxk/cn20k_tls.c     | 47 +++++++++++++++++++++++------
>  drivers/crypto/cnxk/cn20k_tls.h     | 15 ++++++---
>  drivers/crypto/cnxk/cn20k_tls_ops.h |  6 +++-
>  5 files changed, 60 insertions(+), 17 deletions(-)
> 
Series applied to dpdk-next-crypto