[PATCH v1 1/4] net/axgbe: fix MAC TCR speed select field width

[Ashok Kumar Natarajan]

The MAC Transmit Configuration Register (TCR) speed select (SS)
field is defined as 2 bits wide, while the hardware specification
defines this field as 3 bits to encode all supported MAC speeds.

Update the SS field width to 3 bits to match the hardware
specification and avoid truncation of speed select values.

Fixes: 69e209be5464 ("net/axgbe: add register map and related macros")
Cc: stable at dpdk.org

Signed-off-by: Ashok Kumar Natarajan <ashokkumar.natarajan at amd.com>
---
 drivers/net/axgbe/axgbe_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 0bceff5774..842077d972 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -492,7 +492,7 @@
 #define MAC_SSIR_SSINC_INDEX		16
 #define MAC_SSIR_SSINC_WIDTH		8
 #define MAC_TCR_SS_INDEX		29
-#define MAC_TCR_SS_WIDTH		2
+#define MAC_TCR_SS_WIDTH		3
 #define MAC_TCR_TE_INDEX		0
 #define MAC_TCR_TE_WIDTH		1
 #define MAC_TSCR_AV8021ASMEN_INDEX	28
-- 
2.34.1