[PATCH v1 1/4] net/axgbe: fix MAC TCR speed select field width

[Stephen Hemminger]

On Fri, 27 Mar 2026 17:50:03 +0530
Ashok Kumar Natarajan <ashokkumar.natarajan at amd.com> wrote:

> The MAC Transmit Configuration Register (TCR) speed select (SS)
> field is defined as 2 bits wide, while the hardware specification
> defines this field as 3 bits to encode all supported MAC speeds.
> 
> Update the SS field width to 3 bits to match the hardware
> specification and avoid truncation of speed select values.
> 
> Fixes: 69e209be5464 ("net/axgbe: add register map and related macros")
> Cc: stable at dpdk.org
> 
> Signed-off-by: Ashok Kumar Natarajan <ashokkumar.natarajan at amd.com>
> ---

Applied to next-net