[PATCH v4-S3 54/65] event/dpaa2: fix DQRR held buffer accounting on enqueue

[Prashant Gupta]

From: Jun Yang <jun.yang at nxp.com>

In the atomic enqueue path, the DQRR held-buffer state (dqrr_size and
dqrr_held) was updated while building the enqueue descriptors, before
the frames were actually enqueued to the hardware. If the subsequent
qbman_swp_enqueue_multiple_desc() only accepted a subset of the frames
(or none, requiring a retry), the accounting had already been cleared
for frames that were never sent. This left the held-buffer bookkeeping
out of sync with the DQRR entries still owned by the portal, leading to
premature consumption of DQRR slots and incorrect atomic context
release.

Defer the held-buffer update until after each enqueue reports how many
frames were accepted. The per-slot DQRR size and bitmask are recorded
while preparing the descriptors and applied only for the frames that
were actually enqueued.

Signed-off-by: Jun Yang <jun.yang at nxp.com>
---
 drivers/event/dpaa2/dpaa2_eventdev.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
index 01c71fc0d2..127397e681 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -129,8 +129,9 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
 	struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
 	struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
 	uint16_t num_tx = 0;
+	uint64_t dqrr_held[MAX_TX_RING_SLOTS];
 	int ret;
-	uint8_t dqrr_index;
+	uint8_t dqrr_index, dqrr_size[MAX_TX_RING_SLOTS];
 	const struct rte_event *event;
 	struct dpaa2_queue *dpci_txq[MAX_TX_RING_SLOTS];
 	struct rte_event *ev_tx[MAX_TX_RING_SLOTS];
@@ -180,13 +181,15 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
 			qbman_eq_desc_set_fq(&eqdesc[loop], dpci_txq[loop]->fqid);
 			qbman_eq_desc_set_no_orp(&eqdesc[loop], 0);
 			qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
+			dqrr_held[loop] = 0;
+			dqrr_size[loop] = 0;
 
 			if (event->sched_type == RTE_SCHED_TYPE_ATOMIC &&
 				*dpaa2_seqn(event->mbuf)) {
 				dqrr_index = *dpaa2_seqn(event->mbuf) - 1;
 				qbman_eq_desc_set_dca(&eqdesc[loop], 1, dqrr_index, 0);
-				dpio_dev->dpaa2_held_bufs.dqrr_size--;
-				dpio_dev->dpaa2_held_bufs.dqrr_held &= ~(1 << dqrr_index);
+				dqrr_size[loop] = 1;
+				dqrr_held[loop] = UINT64_C(1) << dqrr_index;
 			}
 
 			memset(&fd_arr[loop], 0, sizeof(struct qbman_fd));
@@ -218,6 +221,10 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
 					goto quit;
 				}
 			} else {
+				for (i = loop; i < (loop + ret); i++) {
+					dpio_dev->dpaa2_held_bufs.dqrr_size -= dqrr_size[i];
+					dpio_dev->dpaa2_held_bufs.dqrr_held &= ~dqrr_held[i];
+				}
 				loop += ret;
 				retry_count = 0;
 			}
-- 
2.43.0