[PATCH v4-S3 56/65] bus/fslmc: use explicit flags for mbuf seqn encoding

[Prashant Gupta]

From: Jun Yang <jun.yang at nxp.com>

The DPAA2 drivers stash the DQRR index in the mbuf dynamic seqn field to
support atomic (DCA) and ordered (ORP) enqueue. The index was stored as
"dqrr_index + 1" and the field was tested for a non-zero value to decide
whether it was valid, with the index recovered as "seqn - 1".

This offset-by-one scheme overloads a single field and cannot
distinguish the DCA case from the ORP case; it only works because any
valid index becomes non-zero. It is fragile and makes the DCA and ORP
paths ambiguous.

Encode the seqn using the explicit qbman flag bits instead:
  - store the index as "dqrr_index | QBMAN_ENQUEUE_FLAG_DCA"
  - recover the index with "& QBMAN_EQCR_DCA_IDXMASK"
  - gate the DCA path on "& QBMAN_ENQUEUE_FLAG_DCA"
  - gate the ORP path on "& DPAA2_ENQUEUE_FLAG_ORP"

Apply this consistently across net/dpaa2, crypto/dpaa2_sec and
event/dpaa2 so the atomic and ordered enqueue paths are selected
unambiguously.

Signed-off-by: Jun Yang <jun.yang at nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 17 +++++++----------
 drivers/event/dpaa2/dpaa2_eventdev.c        |  6 +++---
 drivers/net/dpaa2/dpaa2_rxtx.c              |  8 ++++----
 3 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index e34ca884fe..54881bc38c 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -1549,13 +1549,10 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
 			dpaa2_eqcr_size : nb_ops;
 
 		for (loop = 0; loop < frames_to_send; loop++) {
-			if (*dpaa2_seqn((*ops)->sym->m_src)) {
-				if (*dpaa2_seqn((*ops)->sym->m_src) & QBMAN_ENQUEUE_FLAG_DCA) {
-					DPAA2_PER_LCORE_DQRR_SIZE--;
-					DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) <<
-						*dpaa2_seqn((*ops)->sym->m_src) &
-					QBMAN_EQCR_DCA_IDXMASK);
-				}
+			if (*dpaa2_seqn((*ops)->sym->m_src) & QBMAN_ENQUEUE_FLAG_DCA) {
+				DPAA2_PER_LCORE_DQRR_SIZE--;
+				DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) <<
+					*dpaa2_seqn((*ops)->sym->m_src) & QBMAN_EQCR_DCA_IDXMASK);
 				flags[loop] = *dpaa2_seqn((*ops)->sym->m_src);
 				*dpaa2_seqn((*ops)->sym->m_src) = DPAA2_INVALID_MBUF_SEQN;
 			}
@@ -1848,7 +1845,7 @@ dpaa2_sec_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q,
 			qbman_eq_desc_set_orp(eqdesc, 0, orpid, seqnum, 0);
 		}
 	} else {
-		dq_idx = *dpaa2_seqn(m) - 1;
+		dq_idx = *dpaa2_seqn(m) & QBMAN_EQCR_DCA_IDXMASK;
 		qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);
 		DPAA2_PER_LCORE_DQRR_SIZE--;
 		DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dq_idx);
@@ -1897,7 +1894,7 @@ dpaa2_sec_enqueue_burst_ordered(void *qp, struct rte_crypto_op **ops,
 			dpaa2_eqcr_size : nb_ops;
 
 		if (!priv->en_loose_ordered) {
-			if (*dpaa2_seqn((*ops)->sym->m_src)) {
+			if (*dpaa2_seqn((*ops)->sym->m_src) & DPAA2_ENQUEUE_FLAG_ORP) {
 				num_free_eq_desc = dpaa2_free_eq_descriptors();
 				if (num_free_eq_desc < frames_to_send)
 					frames_to_send = num_free_eq_desc;
@@ -1909,7 +1906,7 @@ dpaa2_sec_enqueue_burst_ordered(void *qp, struct rte_crypto_op **ops,
 			qbman_eq_desc_clear(&eqdesc[loop]);
 			qbman_eq_desc_set_fq(&eqdesc[loop], dpaa2_qp->tx_vq.fqid);
 
-			if (*dpaa2_seqn((*ops)->sym->m_src))
+			if (*dpaa2_seqn((*ops)->sym->m_src) & DPAA2_ENQUEUE_FLAG_ORP)
 				dpaa2_sec_set_enqueue_descriptor(
 						&dpaa2_qp->tx_vq,
 						(*ops)->sym->m_src,
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
index 127397e681..2efdbb8b59 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -185,8 +185,8 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
 			dqrr_size[loop] = 0;
 
 			if (event->sched_type == RTE_SCHED_TYPE_ATOMIC &&
-				*dpaa2_seqn(event->mbuf)) {
-				dqrr_index = *dpaa2_seqn(event->mbuf) - 1;
+				(*dpaa2_seqn(event->mbuf) & QBMAN_ENQUEUE_FLAG_DCA)) {
+				dqrr_index = *dpaa2_seqn(event->mbuf) & QBMAN_EQCR_DCA_IDXMASK;
 				qbman_eq_desc_set_dca(&eqdesc[loop], 1, dqrr_index, 0);
 				dqrr_size[loop] = 1;
 				dqrr_held[loop] = UINT64_C(1) << dqrr_index;
@@ -273,7 +273,7 @@ static void dpaa2_eventdev_process_atomic(struct dpaa2_dpio_dev *dpio_dev,
 
 	rte_memcpy(ev, rx_ev, sizeof(struct rte_event));
 	rte_mempool_put(rxq->env_pool, rx_ev);
-	*dpaa2_seqn(ev->mbuf) = dqrr_index + 1;
+	*dpaa2_seqn(ev->mbuf) = dqrr_index | QBMAN_ENQUEUE_FLAG_DCA;
 	dpio_dev->dpaa2_held_bufs.dqrr_size++;
 	dpio_dev->dpaa2_held_bufs.dqrr_held |= UINT64_C(1) << dqrr_index;
 	dpio_dev->dpaa2_held_bufs.mbuf[dqrr_index] = ev->mbuf;
diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index 4f712ec9f7..dfd359d0e2 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -1234,7 +1234,7 @@ dpaa2_dev_process_atomic_event(struct dpaa2_dpio_dev *dpio_dev,
 		ev->mbuf = dpaa2_eth_fd_to_mbuf(rxq->eth_data->dev_private, fd);
 
 	dqrr_index = qbman_get_dqrr_idx(dq);
-	*dpaa2_seqn(ev->mbuf) = dqrr_index + 1;
+	*dpaa2_seqn(ev->mbuf) = dqrr_index | QBMAN_ENQUEUE_FLAG_DCA;
 	dpio_dev->dpaa2_held_bufs.dqrr_size++;
 	dpio_dev->dpaa2_held_bufs.dqrr_held |= UINT64_C(1) << dqrr_index;
 	dpio_dev->dpaa2_held_bufs.mbuf[dqrr_index] = ev->mbuf;
@@ -1570,8 +1570,8 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 		dpaa2_eqcr_size : nb_pkts;
 
 	for (loop = 0; loop < frames_to_send; loop++) {
-		if (*dpaa2_seqn(*bufs)) {
-			uint8_t dqrr_index = *dpaa2_seqn(*bufs) - 1;
+		if (*dpaa2_seqn(*bufs) & QBMAN_ENQUEUE_FLAG_DCA) {
+			uint8_t dqrr_index = *dpaa2_seqn(*bufs) & QBMAN_EQCR_DCA_IDXMASK;
 
 			flags[loop] = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index;
 			DPAA2_PER_LCORE_DQRR_SIZE--;
@@ -1743,7 +1743,7 @@ dpaa2_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q,
 			qbman_eq_desc_set_orp(eqdesc, 0, orpid, seqnum, 0);
 		}
 	} else {
-		dq_idx = *dpaa2_seqn(m) - 1;
+		dq_idx = *dpaa2_seqn(m) & QBMAN_EQCR_DCA_IDXMASK;
 		qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);
 		DPAA2_PER_LCORE_DQRR_SIZE--;
 		DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dq_idx);
-- 
2.43.0