[PATCH v5 06/28] net/hinic3: clear stale Rx hardware CI on queue reset

[Jiacheng Ye]

In compact CQE mode the driver relies on the hardware CI written back by
the NIC to decide whether a completion is pending. The hardware does not
clear that write-back memory on reset, so after a port stop/start the
stale value left by the previous session makes the driver take the whole
ring as completed and report q_depth spurious packets when the next
packet arrives.

Clear the CI write-back memory in hinic3_reset_rx_queue() and add a
memory fence, so the cleared value is visible before the ring is
re-armed.

Fixes: c1537bf6c033 ("net/hinic3: support Compact CQE in init")
Signed-off-by: Jiacheng Ye <yejiacheng4 at h-partners.com>
---
 drivers/net/hinic3/hinic3_ethdev.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/hinic3/hinic3_ethdev.c b/drivers/net/hinic3/hinic3_ethdev.c
index eb5ddd9de6..6c09d6e80d 100644
--- a/drivers/net/hinic3/hinic3_ethdev.c
+++ b/drivers/net/hinic3/hinic3_ethdev.c
@@ -884,6 +884,16 @@ hinic3_reset_rx_queue(struct rte_eth_dev *dev)
 		rxq->prod_idx = 0;
 		rxq->delta = rxq->q_depth;
 		rxq->next_to_update = 0;
+
+		/*
+		 * Hardware does not clear the CI write-back memory on reset, so
+		 * the stale hw_ci must be cleared as well, otherwise the driver
+		 * may treat queued mbufs as completed after restart.
+		 */
+		if (rxq->rq_ci != NULL) {
+			memset(rxq->rq_ci, 0, sizeof(*rxq->rq_ci));
+			rte_atomic_thread_fence(rte_memory_order_seq_cst);
+		}
 	}
 }
 
-- 
2.33.0