[PATCH 1/2] drivers: align cn20k TIM chunk buffers
pbhagavatula at marvell.com
pbhagavatula at marvell.com
Wed Sep 9 04:00:10 CEST 2026
From: Pavan Nikhilesh <pbhagavatula at marvell.com>
cn20k timer needs chunk buffers to be 256B aligned. Align the chunk
buffer header and size.
Update HWWQE response types and base code.
Signed-off-by: Pavan Nikhilesh <pbhagavatula at marvell.com>
---
drivers/common/cnxk/hw/tim.h | 2 +-
drivers/common/cnxk/roc_mbox.h | 11 ++++-
drivers/common/cnxk/roc_tim.c | 5 +-
drivers/common/cnxk/roc_tim.h | 4 +-
drivers/event/cnxk/cnxk_tim_evdev.c | 71 +++++++++++++++-------------
drivers/event/cnxk/cnxk_tim_evdev.h | 1 +
drivers/event/cnxk/cnxk_tim_worker.h | 5 +-
7 files changed, 58 insertions(+), 41 deletions(-)
diff --git a/drivers/common/cnxk/hw/tim.h b/drivers/common/cnxk/hw/tim.h
index 75700a11b868..4333256ab836 100644
--- a/drivers/common/cnxk/hw/tim.h
+++ b/drivers/common/cnxk/hw/tim.h
@@ -56,6 +56,6 @@
#define TIM_MIN_BUCKET_SIZE 1
#define TIM_BUCKET_WRAP_SIZE 3
#define TIM_BUCKET_MIN_GAP 1
-#define TIM_NPA_TMO 0xFFFF
+#define TIM_NPA_TMO 0
#endif /* __TIM_HW_H__ */
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 52ecde656378..f5ea84b7341e 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -3196,7 +3196,9 @@ struct tim_config_req {
uint32_t __io chunksize;
uint32_t __io interval_lo;
uint8_t __io gpioedge;
- uint8_t __io rsvd[3];
+ uint8_t __io priority : 1;
+ uint8_t __io rsvd8 : 7;
+ uint8_t __io rsvd[2];
uint32_t __io interval_hi;
uint64_t __io intervalns;
uint64_t __io clockfreq;
@@ -3222,7 +3224,12 @@ struct tim_feat_info {
uint8_t __io engines;
uint8_t __io hwwqe : 1;
uint8_t __io intvl_ext : 1;
- uint8_t __io rsvd8[4];
+ uint16_t __io max_prd_timers;
+#define TIM_HWWQE_VER_0 0
+#define TIM_HWWQE_VER_1 1
+ uint8_t __io hwwqe_ver : 4;
+ uint8_t __io rsvd4 : 4;
+ uint8_t __io rsvd8;
uint64_t __io rsvd[2];
};
diff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c
index a1461fedb1b4..54204c10783b 100644
--- a/drivers/common/cnxk/roc_tim.c
+++ b/drivers/common/cnxk/roc_tim.c
@@ -194,8 +194,8 @@ roc_tim_lf_base_get(struct roc_tim *roc_tim, uint8_t ring_id)
int
roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, enum roc_tim_clk_src clk_src,
- uint8_t ena_periodic, uint8_t ena_dfb, uint32_t bucket_sz, uint32_t chunk_sz,
- uint64_t interval, uint64_t intervalns, uint64_t clockfreq)
+ uint8_t ena_periodic, uint8_t ena_dfb, uint8_t prio, uint32_t bucket_sz,
+ uint32_t chunk_sz, uint64_t interval, uint64_t intervalns, uint64_t clockfreq)
{
struct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);
struct dev *dev = &sso->dev;
@@ -217,6 +217,7 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, enum roc_tim_clk_src
req->interval_hi = interval >> 32;
req->intervalns = intervalns;
req->clockfreq = clockfreq;
+ req->priority = prio;
req->gpioedge = TIM_GPIO_LTOH_TRANS;
rc = mbox_process(mbox);
diff --git a/drivers/common/cnxk/roc_tim.h b/drivers/common/cnxk/roc_tim.h
index 2eb6e6962bd1..d6302585f37e 100644
--- a/drivers/common/cnxk/roc_tim.h
+++ b/drivers/common/cnxk/roc_tim.h
@@ -47,8 +47,8 @@ int __roc_api roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id,
int __roc_api roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id);
int __roc_api roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,
enum roc_tim_clk_src clk_src, uint8_t ena_periodic, uint8_t ena_dfb,
- uint32_t bucket_sz, uint32_t chunk_sz, uint64_t interval,
- uint64_t intervalns, uint64_t clockfreq);
+ uint8_t prio, uint32_t bucket_sz, uint32_t chunk_sz,
+ uint64_t interval, uint64_t intervalns, uint64_t clockfreq);
int __roc_api roc_tim_lf_config_hwwqe(struct roc_tim *roc_tim, uint8_t ring_id,
struct roc_tim_hwwqe_cfg *cfg);
int __roc_api roc_tim_lf_interval(struct roc_tim *roc_tim,
diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c
index 8cdb8a72dd3c..75414408776d 100644
--- a/drivers/event/cnxk/cnxk_tim_evdev.c
+++ b/drivers/event/cnxk/cnxk_tim_evdev.c
@@ -18,6 +18,7 @@ cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring,
{
unsigned int mp_flags = 0;
unsigned int cache_sz;
+ const char *ops;
char pool_name[25];
int rc;
@@ -33,41 +34,43 @@ cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring,
cache_sz = CNXK_TIM_MAX_POOL_CACHE_SZ;
tim_ring->nb_chunks += (cache_sz * rte_lcore_count());
- if (!tim_ring->disable_npa) {
- tim_ring->chunk_pool = rte_mempool_create_empty(
- pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,
- cache_sz, 0, rte_socket_id(), mp_flags);
- if (tim_ring->chunk_pool == NULL) {
- plt_err("Unable to create chunkpool.");
- return -ENOMEM;
- }
+ tim_ring->chunk_pool = rte_mempool_create_empty(pool_name, tim_ring->nb_chunks,
+ tim_ring->chunk_sz, cache_sz, 0,
+ rte_socket_id(), mp_flags);
+ if (tim_ring->chunk_pool == NULL) {
+ plt_err("Unable to create chunkpool.");
+ return -ENOMEM;
+ }
- rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
- rte_mbuf_platform_mempool_ops(),
- NULL);
- if (rc < 0) {
- plt_err("Unable to set chunkpool ops");
- goto free;
- }
+ /* cn20k needs 256B-aligned chunk buffers (cn20k-tim 14.2). */
+ if (roc_model_is_cn20k())
+ tim_ring->chunk_pool->header_size = RTE_ALIGN_CEIL(
+ tim_ring->chunk_pool->header_size, CNXK_TIM_CN20K_CHUNK_BUF_ALIGN);
- rc = rte_mempool_populate_default(tim_ring->chunk_pool);
- if (rc < 0) {
- plt_err("Unable to set populate chunkpool.");
- goto free;
- }
- tim_ring->aura = roc_npa_aura_handle_to_aura(
- tim_ring->chunk_pool->pool_id);
+ if (!tim_ring->disable_npa)
+ ops = rte_mbuf_platform_mempool_ops();
+ else if (mp_flags & RTE_MEMPOOL_F_SP_PUT)
+ ops = "ring_sp_sc";
+ else
+ ops = "ring_mp_mc";
+
+ rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool, ops, NULL);
+ if (rc < 0) {
+ plt_err("Unable to set chunkpool ops");
+ goto free;
+ }
+
+ rc = rte_mempool_populate_default(tim_ring->chunk_pool);
+ if (rc < 0) {
+ plt_err("Unable to populate chunkpool.");
+ goto free;
+ }
+
+ if (!tim_ring->disable_npa) {
+ tim_ring->aura = roc_npa_aura_handle_to_aura(tim_ring->chunk_pool->pool_id);
tim_ring->ena_dfb = tim_ring->ena_periodic ? 1 : 0;
} else {
- tim_ring->chunk_pool = rte_mempool_create(
- pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,
- cache_sz, 0, NULL, NULL, NULL, NULL, rte_socket_id(),
- mp_flags);
- if (tim_ring->chunk_pool == NULL) {
- plt_err("Unable to create chunkpool.");
- return -ENOMEM;
- }
tim_ring->ena_dfb = 1;
}
@@ -250,6 +253,10 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
}
}
+ if (roc_model_is_cn20k())
+ tim_ring->chunk_sz =
+ RTE_ALIGN_CEIL(tim_ring->chunk_sz, CNXK_TIM_CN20K_CHUNK_BUF_ALIGN);
+
if (!dev->tim.feat.hwwqe && tim_ring->disable_npa) {
tim_ring->nb_chunks =
tim_ring->nb_timers /
@@ -274,7 +281,7 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
goto tim_bkt_free;
rc = roc_tim_lf_config(&dev->tim, tim_ring->ring_id, clk_src,
- tim_ring->ena_periodic, tim_ring->ena_dfb,
+ tim_ring->ena_periodic, tim_ring->ena_dfb, 0,
tim_ring->nb_bkts, tim_ring->chunk_sz,
tim_ring->tck_int, tim_ring->tck_nsec, clk_freq);
if (rc < 0) {
@@ -282,7 +289,7 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
goto tim_chnk_free;
}
- if (dev->tim.feat.hwwqe) {
+ if (dev->tim.feat.hwwqe && dev->tim.feat.hwwqe_ver != TIM_HWWQE_VER_0) {
rc = cnxk_tim_enable_hwwqe(dev, tim_ring);
if (rc < 0) {
plt_err("Failed to enable hwwqe");
diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h
index 114a89ee5aec..83e9cfd458fb 100644
--- a/drivers/event/cnxk/cnxk_tim_evdev.h
+++ b/drivers/event/cnxk/cnxk_tim_evdev.h
@@ -25,6 +25,7 @@
#define CNXK_TIM_MAX_BUCKETS (0xFFFFF)
#define CNXK_TIM_RING_DEF_CHUNK_SZ (1024)
#define CNXK_TIM_CHUNK_ALIGNMENT (16)
+#define CNXK_TIM_CN20K_CHUNK_BUF_ALIGN (256)
#define CNXK_TIM_MAX_BURST (16)
#define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1)
#define CNXK_TIM_MIN_CHUNK_SLOTS (0x1)
diff --git a/drivers/event/cnxk/cnxk_tim_worker.h b/drivers/event/cnxk/cnxk_tim_worker.h
index 09f84091abba..6a9099a23f3a 100644
--- a/drivers/event/cnxk/cnxk_tim_worker.h
+++ b/drivers/event/cnxk/cnxk_tim_worker.h
@@ -625,14 +625,15 @@ cnxk_tim_add_entry_hwwqe(struct cnxk_tim_ring *const tim_ring, struct rte_event_
rsp >>= 4;
switch (rsp) {
case 0x3:
- tim->state = RTE_EVENT_TIMER_ERROR_TOOEARLY;
+ tim->state = RTE_EVENT_TIMER_ERROR_TOOLATE;
rc = !rc;
break;
case 0x4:
- tim->state = RTE_EVENT_TIMER_ERROR_TOOLATE;
+ tim->state = RTE_EVENT_TIMER_ERROR_TOOEARLY;
rc = !rc;
break;
case 0x1:
+ case 0x5:
tim->state = RTE_EVENT_TIMER_ARMED;
break;
default:
--
2.50.1 (Apple Git-155)
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