[EXTERNAL] [PATCH v2] common/cnxk: fix NPA pool RANGE interrupt handling

Ashwin Sekhar asekhar at marvell.com
Wed Sep 16 19:46:37 CEST 2026


> On AQ Init, the context is first allocated in the cache. -> Does the hardware take care of it? Before writing to memory, it writes to NDC first?
Yes. The hardware takes care.

 


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