[PATCH v2 3/4] dma/cnxk: enable inter process domain DMA support

[Vamsi Krishna]

From: Vamsi Attunuru <vattunuru at marvell.com>

Adds support for inter domain DMA operations.

Signed-off-by: Vamsi Attunuru <vattunuru at marvell.com>
---
 doc/guides/dmadevs/cnxk.rst    |  73 ++++++++++++++++
 drivers/dma/cnxk/cnxk_dmadev.c | 148 ++++++++++++++++++++++++++++++++-
 drivers/dma/cnxk/cnxk_dmadev.h |   1 +
 3 files changed, 221 insertions(+), 1 deletion(-)

diff --git a/doc/guides/dmadevs/cnxk.rst b/doc/guides/dmadevs/cnxk.rst
index 2794f393a7..9021a0f126 100644
--- a/doc/guides/dmadevs/cnxk.rst
+++ b/doc/guides/dmadevs/cnxk.rst
@@ -110,6 +110,79 @@ Refer to the :ref:`dmadev_enqueue_dequeue` section
 of the dmadev library documentation
 for details on operation enqueue and submission API usage.
 
+CN20K inter-process domain DMA transfers
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+CN20K DPI devices advertise the ``RTE_DMA_CAPA_INTER_PROCESS_DOMAIN`` capability.
+This enables DMA transfers between memory owned by different DPDK processes
+running on the same CN20K SoC.
+
+Each participating process must bind its own CN20K DPI PF or VF device to
+``vfio-pci`` and probe it through the ``cnxk`` dmadev PMD.
+Inter-process domain transfers are supported only with
+``RTE_DMA_DIR_MEM_TO_MEM`` direction.
+
+Access pair group setup
+^^^^^^^^^^^^^^^^^^^^^^^
+
+Before configuring a virtual channel for inter-process DMA, each process must
+join a common access pair group using the dmadev access pair group API.
+The general setup flow is described in
+:doc:`/prog_guide/dmadev` under *Inter-domain DMA Transfers*.
+
+At a high level:
+
+#. Each process generates a unique ``domain_id`` (``rte_uuid_t``) to identify
+   its process domain.
+#. Process#1 generates a ``token`` and calls ``rte_dma_access_pair_group_create()``.
+#. Process#1 shares the ``group_id``, ``token`` and its ``domain_id`` with
+   Process#2 through an out-of-band channel.
+#. Process#2 calls ``rte_dma_access_pair_group_join()`` with the shared
+   ``group_id``, ``token`` and its own ``domain_id``.
+#. Each process retrieves source and destination handler values using
+   ``rte_dma_access_pair_group_handler_get()``.
+#. Each process configures its virtual channel and performs DMA transfers.
+#. Process#2 calls ``rte_dma_access_pair_group_leave()`` when finished.
+#. Process#1 calls ``rte_dma_access_pair_group_destroy()`` to tear down the group.
+
+Virtual channel configuration
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+After the access pair group is established and handler values are exchanged,
+configure the virtual channel with ``RTE_DMA_INTER_PROCESS_DOMAIN`` domain type.
+For example::
+
+     struct rte_dma_vchan_conf vchan_conf = {0};
+
+     vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
+     vchan_conf.nb_desc = 128;
+     vchan_conf.domain.type = RTE_DMA_INTER_PROCESS_DOMAIN;
+     vchan_conf.domain.src_handler = local_src_handler;
+     vchan_conf.domain.dst_handler = peer_dst_handler;
+
+     rte_dma_vchan_setup(dma_dev_id, vchan, &vchan_conf);
+
+``src_handler``
+
+  Handler for the local process domain, obtained from
+  ``rte_dma_access_pair_group_handler_get()`` using the local domain_id.
+
+``dst_handler``
+
+  Handler for the peer process domain, obtained from
+  ``rte_dma_access_pair_group_handler_get()`` using the peer domain_id.
+
+Once the virtual channel is configured, start the device and issue copy or
+copy-SG operations as for a regular memory-to-memory transfer.
+
+.. note::
+
+   Inter-process domain DMA is supported on CN20K only.
+   CN9K/CN10K DPI devices do not advertise
+   ``RTE_DMA_CAPA_INTER_PROCESS_DOMAIN``.
+
+   The access pair group APIs are experimental and may change in future releases.
+
 Performance Tuning Parameters
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
index 602241d755..db177afd6f 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.c
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -98,7 +98,7 @@ cnxk_dmadev_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *dev_inf
 		dev_info->min_desc = CN20K_DPI_MIN_DESC;
 		dev_info->max_sges = CN20K_DPI_MAX_POINTER;
 		dev_info->max_vchans = dpivf->max_vchans;
-		dev_info->dev_capa |= RTE_DMA_CAPA_OPS_FILL;
+		dev_info->dev_capa |= (RTE_DMA_CAPA_OPS_FILL | RTE_DMA_CAPA_INTER_PROCESS_DOMAIN);
 	} else {
 		dev_info->max_desc = CNXK_DPI_MAX_DESC;
 		dev_info->min_desc = CNXK_DPI_MIN_DESC;
@@ -443,6 +443,13 @@ cn20k_dmadev_setup(struct cnxk_dpi_vf_s *dpivf, uint16_t vchan,
 		break;
 	case RTE_DMA_DIR_MEM_TO_MEM:
 		dpi_conf->cfg.xtype = DPI_XTYPE_INTERNAL_ONLY;
+		if (conf->domain.type == RTE_DMA_INTER_PROCESS_DOMAIN) {
+			dpi_conf->chan_cfg.type = RTE_DMA_INTER_PROCESS_DOMAIN;
+			dpi_conf->chan_cfg.src_key = conf->domain.src_handler;
+			dpi_conf->chan_cfg.dst_key = conf->domain.dst_handler;
+			header->cn20k.chan = CNXK_DPI_SRC_DST_KEY(dpi_conf->chan_cfg.src_key,
+								  dpi_conf->chan_cfg.dst_key);
+		}
 		dpi_conf->cfg.rport = 0;
 		dpi_conf->cfg.wport = 0;
 		break;
@@ -1016,6 +1023,140 @@ cnxk_set_fp_ops(struct rte_dma_dev *dev, uint8_t ena_enq_deq)
 	}
 }
 
+static int
+cnxk_dmadev_access_pair_group_create(const struct rte_dma_dev *dev, rte_uuid_t domain_id,
+				       rte_uuid_t token, int16_t *group_id,
+				       rte_dma_access_pair_group_event_cb_t cb)
+{
+	struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+	struct roc_dpi_lf *lf;
+	int rc;
+
+	RTE_SET_USED(cb);
+
+	if (!roc_model_is_cn20k())
+		return -ENOTSUP;
+
+	if (dpivf->rdpi.lfs == NULL || dpivf->rdpi.nr_lfs == 0) {
+		plt_err("DPI LF resources are not initialized");
+		return -EINVAL;
+	}
+
+	lf = &(dpivf->rdpi.lfs[0]);
+
+	rc = roc_dpi_access_pair_group_create(lf, domain_id, token, group_id);
+
+	return rc;
+}
+
+static int
+cnxk_dmadev_access_pair_group_destroy(const struct rte_dma_dev *dev, int16_t group_id)
+{
+	struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+	struct roc_dpi_lf *lf;
+	int rc;
+
+	if (!roc_model_is_cn20k())
+		return -ENOTSUP;
+
+	if (dpivf->rdpi.lfs == NULL || dpivf->rdpi.nr_lfs == 0) {
+		plt_err("DPI LF resources are not initialized");
+		return -EINVAL;
+	}
+
+	lf = &(dpivf->rdpi.lfs[0]);
+
+	if (lf->group_id != group_id) {
+		plt_err("Invalid access pair group is passed");
+		return -EINVAL;
+	}
+
+	rc = roc_dpi_access_pair_group_destroy(lf, group_id);
+
+	return rc;
+}
+
+static int
+cnxk_dmadev_access_pair_group_join(const struct rte_dma_dev *dev, rte_uuid_t domain_id,
+				   rte_uuid_t token, int16_t group_id,
+				   rte_dma_access_pair_group_event_cb_t cb)
+{
+	struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+	struct roc_dpi_lf *lf;
+	int rc;
+
+	RTE_SET_USED(cb);
+
+	if (!roc_model_is_cn20k())
+		return -ENOTSUP;
+
+	if (dpivf->rdpi.lfs == NULL || dpivf->rdpi.nr_lfs == 0) {
+		plt_err("DPI LF resources are not initialized");
+		return -EINVAL;
+	}
+
+	lf = &(dpivf->rdpi.lfs[0]);
+
+	rc = roc_dpi_access_pair_group_join(lf, domain_id, token, group_id);
+
+	return rc;
+}
+
+static int
+cnxk_dmadev_access_pair_group_leave(const struct rte_dma_dev *dev, int16_t group_id)
+{
+	struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+	struct roc_dpi_lf *lf;
+	int rc;
+
+	if (!roc_model_is_cn20k())
+		return -ENOTSUP;
+
+	if (dpivf->rdpi.lfs == NULL || dpivf->rdpi.nr_lfs == 0) {
+		plt_err("DPI LF resources are not initialized");
+		return -EINVAL;
+	}
+
+	lf = &(dpivf->rdpi.lfs[0]);
+
+	if (lf->group_id != group_id) {
+		plt_err("Invalid access pair group is passed");
+		return -EINVAL;
+	}
+
+	rc = roc_dpi_access_pair_group_leave(lf, group_id);
+
+	return rc;
+}
+
+static int
+cnxk_dmadev_access_pair_group_handler_get(const struct rte_dma_dev *dev, int16_t group_id,
+					  rte_uuid_t domain_id, uint16_t *handler)
+{
+	struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+	struct roc_dpi_lf *lf;
+	int rc;
+
+	if (!roc_model_is_cn20k())
+		return -ENOTSUP;
+
+	if (dpivf->rdpi.lfs == NULL || dpivf->rdpi.nr_lfs == 0) {
+		plt_err("DPI LF resources are not initialized");
+		return -EINVAL;
+	}
+
+	lf = &(dpivf->rdpi.lfs[0]);
+
+	if (lf->group_id != group_id) {
+		plt_err("Invalid access pair group is passed");
+		return -EINVAL;
+	}
+
+	rc = roc_dpi_access_pair_group_handler_get(lf, group_id, domain_id, handler);
+
+	return rc;
+}
+
 static const struct rte_dma_dev_ops cnxk_dmadev_ops = {
 	.dev_close = cnxk_dmadev_close,
 	.dev_configure = cnxk_dmadev_configure,
@@ -1025,6 +1166,11 @@ static const struct rte_dma_dev_ops cnxk_dmadev_ops = {
 	.stats_get = cnxk_stats_get,
 	.stats_reset = cnxk_stats_reset,
 	.vchan_setup = cnxk_dmadev_vchan_setup,
+	.access_pair_group_create = cnxk_dmadev_access_pair_group_create,
+	.access_pair_group_destroy = cnxk_dmadev_access_pair_group_destroy,
+	.access_pair_group_join = cnxk_dmadev_access_pair_group_join,
+	.access_pair_group_leave = cnxk_dmadev_access_pair_group_leave,
+	.access_pair_group_handler_get = cnxk_dmadev_access_pair_group_handler_get,
 };
 
 static int
diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
index 3ba404dda8..043f48cb7e 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.h
+++ b/drivers/dma/cnxk/cnxk_dmadev.h
@@ -47,6 +47,7 @@
 							     CNXK_DPI_MAX_POINTER)
 #define CNXK_DPI_CHUNKS_FROM_DESC(cz, desc) (((desc) / (((cz) / 8) / CNXK_DPI_MAX_CMD_SZ)) + 1)
 #define CNXK_DPI_COMPL_OFFSET		    ROC_CACHE_LINE_SZ
+#define CNXK_DPI_SRC_DST_KEY(src, dst)	    ((0x2040) | ((src & 0x3F) << 7) | (dst & 0x3F))
 
 #define CN20K_DPI_MAX_POINTER		    4
 #define CN20K_DPI_MAX_DESC		    2048
-- 
2.34.1