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From patchwork Fri Aug 12 16:52:22 2022
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<div>X-Patchwork-Submitter: "Zhang, Peng1X" <peng1x.zhang@intel.com></div>
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<div>From: peng1x.zhang@intel.com</div>
<div>To: dev@dpdk.org</div>
<div>Cc: beilei.xing@intel.com, jingjing.wu@intel.com,</div>
<div> Peng Zhang <peng1x.zhang@intel.com></div>
<div>Subject: [PATCH 1/2] net/iavf: enable TSO offloading for tunnel cases</div>
<div>Date: Sat, 13 Aug 2022 00:52:22 +0800</div>
<div>Message-Id: <20220812165223.470777-1-peng1x.zhang@intel.com></div>
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<div>From: Peng Zhang <peng1x.zhang@intel.com></div>
<div><br>
</div>
<div>Hardware limits that max buffer size per Tx descriptor should be (16K-1)B.</div>
<div>So when TSO enabled under unencrypt scenario, the mbuf data size may exceed</div>
<div>the limit and cause malicious behavior to the NIC.</div>
<div><br>
</div>
<div>This patch supports Tx descriptors for this kind of large buffer.</div>
<div><br>
</div>
<div>Signed-off-by: Peng Zhang <peng1x.zhang@intel.com></div>
<div>---</div>
<div>Tested-by: Daniel M Buckley <daniel.m.buckley@intel.com></div>
<div><br>
</div>
<div> drivers/net/iavf/iavf_rxtx.c | 66 ++++++++++++++++++++++++++++++++----</div>
<div> 1 file changed, 60 insertions(+), 6 deletions(-)</div>
<div><br>
</div>
<div>diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c</div>
<div>index dfd021889e..adec58e90a 100644</div>
<div>--- a/drivers/net/iavf/iavf_rxtx.c</div>
<div>+++ b/drivers/net/iavf/iavf_rxtx.c</div>
<div>@@ -2642,6 +2642,47 @@ iavf_ipsec_crypto_get_pkt_metadata(const struct iavf_tx_queue *txq,</div>
<div> return NULL;</div>
<div> }</div>
<div> </div>
<div>+/* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */</div>
<div>+#define IAVF_MAX_DATA_PER_TXD \</div>
<div>+ (IAVF_TXD_QW1_TX_BUF_SZ_MASK >> IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)</div>
<div>+</div>
<div>+static inline void</div>
<div>+iavf_fill_unencrypt_desc(volatile struct iavf_tx_desc *txd, struct rte_mbuf *m,</div>
<div>+ volatile uint64_t desc_template, struct iavf_tx_entry *txe,</div>
<div>+ volatile struct iavf_tx_desc *txr, struct iavf_tx_entry *txe_ring,</div>
<div>+ int desc_idx_last)</div>
<div>+{</div>
<div>+ /* Setup TX Descriptor */</div>
<div>+ int desc_idx;</div>
<div>+ uint16_t slen = m->data_len;</div>
<div>+ uint64_t buf_dma_addr = rte_mbuf_data_iova(m);</div>
<div>+ struct iavf_tx_entry *txn = &txe_ring[txe->next_id];</div>
<div>+</div>
<div>+ while ((m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&</div>
<div>+ unlikely(slen > IAVF_MAX_DATA_PER_TXD)) {</div>
<div>+ txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);</div>
<div>+</div>
<div>+ txd->cmd_type_offset_bsz =</div>
<div>+ rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |</div>
<div>+ (uint64_t)IAVF_MAX_DATA_PER_TXD <<</div>
<div>+ IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) | desc_template;</div>
<div>+</div>
<div>+ buf_dma_addr += IAVF_MAX_DATA_PER_TXD;</div>
<div>+ slen -= IAVF_MAX_DATA_PER_TXD;</div>
<div>+</div>
<div>+ txe->last_id = desc_idx_last;</div>
<div>+ desc_idx = txe->next_id;</div>
<div>+ txe = txn;</div>
<div>+ txd = &txr[desc_idx];</div>
<div>+ txn = &txe_ring[txe->next_id];</div>
<div>+ }</div>
<div>+</div>
<div>+ txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);</div>
<div>+ txd->cmd_type_offset_bsz =</div>
<div>+ rte_cpu_to_le_64((uint64_t)slen << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) |</div>
<div>+ desc_template;</div>
<div>+}</div>
<div>+</div>
<div> /* TX function */</div>
<div> uint16_t</div>
<div> iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)</div>
<div>@@ -2650,6 +2691,7 @@ iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)</div>
<div> volatile struct iavf_tx_desc *txr = txq->tx_ring;</div>
<div> struct iavf_tx_entry *txe_ring = txq->sw_ring;</div>
<div> struct iavf_tx_entry *txe, *txn;</div>
<div>+ volatile struct iavf_tx_desc *txd;</div>
<div> struct rte_mbuf *mb, *mb_seg;</div>
<div> uint16_t desc_idx, desc_idx_last;</div>
<div> uint16_t idx;</div>
<div>@@ -2781,6 +2823,7 @@ iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)</div>
<div> ddesc = (volatile struct iavf_tx_desc *)</div>
<div> &txr[desc_idx];</div>
<div> </div>
<div>+ txd = &txr[desc_idx];</div>
<div> txn = &txe_ring[txe->next_id];</div>
<div> RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);</div>
<div> </div>
<div>@@ -2788,10 +2831,16 @@ iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)</div>
<div> rte_pktmbuf_free_seg(txe->mbuf);</div>
<div> </div>
<div> txe->mbuf = mb_seg;</div>
<div>- iavf_fill_data_desc(ddesc, mb_seg,</div>
<div>- ddesc_template, tlen, ipseclen);</div>
<div> </div>
<div>- IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);</div>
<div>+ if (nb_desc_ipsec) {</div>
<div>+ iavf_fill_data_desc(ddesc, mb_seg,</div>
<div>+ ddesc_template, tlen, ipseclen);</div>
<div>+ IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);</div>
<div>+ } else {</div>
<div>+ iavf_fill_unencrypt_desc(txd, mb_seg,</div>
<div>+ ddesc_template, txe, txr, txe_ring, desc_idx_last);</div>
<div>+ IAVF_DUMP_TX_DESC(txq, txd, desc_idx);</div>
<div>+ }</div>
<div> </div>
<div> txe->last_id = desc_idx_last;</div>
<div> desc_idx = txe->next_id;</div>
<div>@@ -2816,10 +2865,15 @@ iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)</div>
<div> txq->nb_used = 0;</div>
<div> }</div>
<div> </div>
<div>- ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<</div>
<div>+ if (nb_desc_ipsec) {</div>
<div>+ ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<</div>
<div> IAVF_TXD_DATA_QW1_CMD_SHIFT);</div>
<div>-</div>
<div>- IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);</div>
<div>+ IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);</div>
<div>+ } else {</div>
<div>+ txd->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<</div>
<div>+ IAVF_TXD_DATA_QW1_CMD_SHIFT);</div>
<div>+ IAVF_DUMP_TX_DESC(txq, txd, desc_idx - 1);</div>
<div>+ }</div>
<div> }</div>
<div> </div>
<div> end_of_tx:</div>
<br>
</div>
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