<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="en-IL" link="#0563C1" vlink="#954F72" style="word-wrap:break-word"> <div class="WordSection1"> Please find below NVIDIA roadmap for 23.03 release:<o:p></o:p> <o:p> </o:p> A. rte_flow new APIs<o:p></o:p> =================<o:p></o:p> [1] Support match on ICMPv6 ID and sequence<o:p></o:p> <a href="https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatches.dpdk.org%2Fproject%2Fdpdk%2Fcover%2F20221220074403.1015411-1-yongquanx%40nvidia.com%2F&data=05%7C01%7Clmargalit%40nvidia.com%7Ccae3c0517aab44ff1eff08daed9f9481%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C638083566891787420%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=UA%2FnSYhayX9RJUVbamMKaHQ2sjKgyBJdaA3L4k72Olg%3D&reserved=0">http://patches.dpdk.org/project/dpdk/cover/20221220074403.1015411-1-yongquanx@nvidia.com/</a><o:p></o:p> Add new pattern item types for ICMPv6 echo request and reply.<o:p></o:p> <o:p></o:p> [2] Support match on port affinity and set affinity in Tx queue<o:p></o:p> <a href="https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatches.dpdk.org%2Fproject%2Fdpdk%2Fcover%2F20221221102934.13822-1-jiaweiw%40nvidia.com%2F&data=05%7C01%7Clmargalit%40nvidia.com%7Ccae3c0517aab44ff1eff08daed9f9481%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C638083566891787420%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=%2Fwkk4A5JmnLejtgBImLOjQsBkn%2FR9THmTncP32DAIPs%3D&reserved=0">http://patches.dpdk.org/project/dpdk/cover/20221221102934.13822-1-jiaweiw@nvidia.com/</a> <o:p></o:p> Value: expose indication in DPDK level to which physical port the packet belongs to. Example of usage: when dual ports configured as a bond in Linux, the app can get the ingress port of a packet, and send the ACK out on the same port.<o:p></o:p> Add new pattern item type for port affinity. Its value reflects the physical port affinity of the received packets. <o:p></o:p> Add tx_affinity setting in Tx queue, the affinity value reflects the physical port the packets will be sent to. <o:p></o:p> <o:p> </o:p> [3] Support specifying the direction info when creating the transfer table. <o:p></o:p> <a href="https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatches.dpdk.org%2Fproject%2Fdpdk%2Fpatch%2F20221114115946.1074787-1-rongweil%40nvidia.com%2F&data=05%7C01%7Clmargalit%40nvidia.com%7Ccae3c0517aab44ff1eff08daed9f9481%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C638083566891787420%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=vb3C78CHi658fjZewTdy9lTh0nBMc2OvqzMeUCXLxOU%3D&reserved=0">http://patches.dpdk.org/project/dpdk/patch/20221114115946.1074787-1-rongweil@nvidia.com/</a> <o:p></o:p> Value: enable memory footprint reduction when creating the HW table entries.<o:p></o:p> Add an option to define the direction (traffic originates from uplink/vport/both) when creating the HW table. <o:p></o:p> <o:p> </o:p> [4] Support match on IPv6 routing extension<o:p></o:p> <a href="https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatches.dpdk.org%2Fproject%2Fdpdk%2Fpatch%2F20221221084304.3680690-2-rongweil%40nvidia.com%2F&data=05%7C01%7Clmargalit%40nvidia.com%7Ccae3c0517aab44ff1eff08daed9f9481%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C638083566891787420%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=21UCpnCZ0P%2Bg2jFB0VRTXUZz2Aa1KwkbJ0XxwwYk%2FBw%3D&reserved=0">http://patches.dpdk.org/project/dpdk/patch/20221221084304.3680690-2-rongweil@nvidia.com/</a> <o:p></o:p> Add new pattern types to match on the presence of IPv6 routing extension header, extension header type, next header and valid segments number. <o:p></o:p> <o:p></o:p> [5] Support setting process as active or standby<o:p></o:p> <a href="https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatches.dpdk.org%2Fproject%2Fdpdk%2Fcover%2F20221221090017.3715030-1-rongweil%40nvidia.com%2F&data=05%7C01%7Clmargalit%40nvidia.com%7Ccae3c0517aab44ff1eff08daed9f9481%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C638083566891787420%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=rz%2FpfGxqvs4I5%2BCL%2BoAl3oaUSsm6Sxf2omXEQXEo9lc%3D&reserved=0">http://patches.dpdk.org/project/dpdk/cover/20221221090017.3715030-1-rongweil@nvidia.com/</a> <o:p></o:p> Value: allow an application to program rules in the HW, but activate them in later time. <o:p></o:p> Example of usage: enable hot upgrade of the application with minimal downtime.<o:p></o:p> The “active” role means rules are programmed to HW immediately, it is the default state.<o:p></o:p> The “standby” role means rules are queued in the HW. When activating the process, the rules become effective immediately.<o:p></o:p> In Nvidia (mlx5) PMD it is done by toggling the priority of the rules in group 0, because this is the root group that is shared by all the applications.<o:p></o:p> <o:p> </o:p> [6] Support Flex item modify field<o:p></o:p> <a href="https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatches.dpdk.org%2Fproject%2Fdpdk%2Fcover%2F20221221084000.3680015-1-rongweil%40nvidia.com%2F&data=05%7C01%7Clmargalit%40nvidia.com%7Ccae3c0517aab44ff1eff08daed9f9481%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C638083566891787420%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=GRnJUjhZHRZ56dXy3fl0v7CZwPAer%2FEGB%2BirNTUci3Y%3D&reserved=0">http://patches.dpdk.org/project/dpdk/cover/20221221084000.3680015-1-rongweil@nvidia.com/</a> <o:p></o:p> Flow flex item provides the capability to introduce an arbitrary user-specified network protocol header.<o:p></o:p> There is already API to perform match on this header with desired patterns and masks, and in this release flex item modify field action is added. <o:p></o:p> <o:p> </o:p> [7] Support sharing indirect actions between ports<o:p></o:p> <a href="https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatches.dpdk.org%2Fproject%2Fdpdk%2Fpatch%2F20221228165433.18185-1-viacheslavo%40nvidia.com%2F&data=05%7C01%7Clmargalit%40nvidia.com%7Ccae3c0517aab44ff1eff08daed9f9481%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C638083566891787420%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=41hA8b%2BuDXH1kmgbD%2FXkVCGM22hSamF4AzLSHw04ryk%3D&reserved=0">https://patches.dpdk.org/project/dpdk/patch/20221228165433.18185-1-viacheslavo@nvidia.com/</a><o:p></o:p> The goal is to manage packets belonging to the same logical connection that may come and go through different ports. <o:p></o:p> Example of use may be with Connection Tracking object that needs to be updated from two different ports; Or - a Quota item (see #A.9) in which the application logic needs to monitor a volume quota that counts both uplink and downlink traffic. This capability is supported for ports that reside in the same physical NIC. <o:p></o:p>  <o:p></o:p> [8] Support template table insertion and matching types<o:p></o:p> <a href="https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatches.dpdk.org%2Fproject%2Fdpdk%2Fpatch%2F20221214022110.393410-1-akozyrev%40nvidia.com%2F&data=05%7C01%7Clmargalit%40nvidia.com%7Ccae3c0517aab44ff1eff08daed9f9481%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C638083566891787420%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=1tz5IPV9iIpJ3zPkKisPsTghFONv6z%2FY1Jki%2FbIONPw%3D&reserved=0">https://patches.dpdk.org/project/dpdk/patch/20221214022110.393410-1-akozyrev@nvidia.com/</a><o:p></o:p> The goal in index-based insertion is providing flexibility in pipeline orchestration and performance improvement, by avoiding additional matches and simply execute predefined actions after jumping to the rule index.<o:p></o:p> Allow a user to specify the insertion type used in template tables. <o:p></o:p> Flow rules can be inserted by calculating the hash value for the pattern or inserted by index. <o:p></o:p> Allow a user to specify the hash calculation function used in template tables (linear, CRC32 and CRC16).<o:p></o:p> The custom hash result can be retrieved via new modify_field id: RTE_FLOW_FIELD_HASH_RESULT<o:p></o:p> <o:p> </o:p> [9] Support Quota flow action and item<o:p></o:p> <a href="https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatches.dpdk.org%2Fproject%2Fdpdk%2Fpatch%2F20221221073547.988-2-getelson%40nvidia.com%2F&data=05%7C01%7Clmargalit%40nvidia.com%7Ccae3c0517aab44ff1eff08daed9f9481%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C638083566891787420%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=ZFH3YOAEyhNSnRxuCFZIrvpKwkAQJ320yXYHjlxMi7k%3D&reserved=0">https://patches.dpdk.org/project/dpdk/patch/20221221073547.988-2-getelson@nvidia.com/</a><o:p></o:p> Value: allow setting a flow or multiple flows to share a volume quota in which traffic usage can be monitored by the application to assure usage is permitted up to a predefined limit<o:p></o:p> The Quota action limits traffic according to pre-defined configuration.<o:p></o:p> The quota action updates the ‘quota’ value and sets packet quota state (PASS or BLOCK).<o:p></o:p> The quota item matches on the flow quota state. <o:p></o:p> <o:p> </o:p> [10] Support LZ4 decompress algorithm in rte_comp<o:p></o:p> <a href="https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.dpdk.org%2Fproject%2Fdpdk%2Fpatch%2F20220410182622.8828-1-rzidane%40nvidia.com%2F&data=05%7C01%7Clmargalit%40nvidia.com%7Ccae3c0517aab44ff1eff08daed9f9481%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C638083566891787420%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=f8O%2FZOkMI0UkBroGXKsN2gqzp2GYBIhvi7JHdrXlqr0%3D&reserved=0">https://patchwork.dpdk.org/project/dpdk/patch/20220410182622.8828-1-rzidane@nvidia.com/</a><o:p></o:p> lz4 is an extremely fast lossless compression algorithm, based on byte-aligned LZ77 family of compression scheme. <o:p></o:p> BlueField-3 Data Processing Unit (DPU) supports decompression for lz4 blocks. <o:p></o:p> More info is here: <a href="https://github.com/lz4/lz4">https://github.com/lz4/lz4</a><o:p></o:p> <o:p> </o:p> B. Net/mlx5 PMD updates<o:p></o:p> =====================<o:p></o:p> [1] Support match on ESP header and SPI field in ESP header for IPSec tunnels.<o:p></o:p> <o:p> </o:p> [2] Support enhanced CQE compression<o:p></o:p> Value: reduce PCI overhead on CQE writes to improve performance.<o:p></o:p> Extend rxq_cqe_comp_en devarg to support enhanced mode for the different layout.<o:p></o:p> <o:p> </o:p> [4] Support Flex item match and modify field through the async API<o:p></o:p> <o:p> </o:p> [3] Support BlueField-3 Data Processing Unit (DPU)<o:p></o:p> <o:p> </o:p> C. Test apps updates <o:p></o:p> ================= <o:p></o:p> [1] Support the changes in rte_flow listed above in testpmd. <o:p></o:p> <o:p> </o:p> [2] Added algo option in test-compress-perf so the user can choose between null(DMA), deflate, lzs or lz4 (default: deflate)<o:p></o:p> <o:p> </o:p> </div> </body> </html>