<div dir="ltr"><div dir="ltr"><div>Recheck-request: iol-sample-apps-testing, </div>This email is a test of the community lab's retesting system, please ignore. Testing superseded reply on a patch. </div> <div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Aug 3, 2023 at 3:51 AM David Marchand <<a href="mailto:david.marchand@redhat.com">david.marchand@redhat.com</a>> wrote: </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Define some PCI command constants and use them in existing drivers. Signed-off-by: David Marchand <<a href="mailto:david.marchand@redhat.com" target="_blank">david.marchand@redhat.com</a>> --- drivers/bus/pci/linux/pci_vfio.c | 8 ++++---- drivers/event/dlb2/pf/dlb2_main.c | 8 +++----- lib/pci/rte_pci.h | 4 +++- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c index 6d13cafdcf..f96b3ce7fb 100644 --- a/drivers/bus/pci/linux/pci_vfio.c +++ b/drivers/bus/pci/linux/pci_vfio.c @@ -156,18 +156,18 @@ pci_vfio_enable_bus_memory(struct rte_pci_device *dev, int dev_fd) return -1; } - ret = pread64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND); + ret = pread64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); if (ret != sizeof(cmd)) { RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n"); return -1; } - if (cmd & PCI_COMMAND_MEMORY) + if (cmd & RTE_PCI_COMMAND_MEMORY) return 0; - cmd |= PCI_COMMAND_MEMORY; - ret = pwrite64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND); + cmd |= RTE_PCI_COMMAND_MEMORY; + ret = pwrite64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); if (ret != sizeof(cmd)) { RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n"); diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index c6606a9bee..6dbaa2ff97 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -33,7 +33,6 @@ #define DLB2_PCI_EXP_DEVCTL2 40 #define DLB2_PCI_LNKCTL2 48 #define DLB2_PCI_SLTCTL2 56 -#define DLB2_PCI_CMD 4 #define DLB2_PCI_EXP_DEVSTA 10 #define DLB2_PCI_EXP_DEVSTA_TRPND 0x20 #define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000 @@ -47,7 +46,6 @@ #define DLB2_PCI_ERR_ROOT_STATUS 0x30 #define DLB2_PCI_ERR_COR_STATUS 0x10 #define DLB2_PCI_ERR_UNCOR_STATUS 0x4 -#define DLB2_PCI_COMMAND_INTX_DISABLE 0x400 #define DLB2_PCI_ACS_CAP 0x4 #define DLB2_PCI_ACS_CTRL 0x6 #define DLB2_PCI_ACS_SV 0x1 @@ -286,7 +284,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) /* clear the PCI command register before issuing the FLR */ - off = DLB2_PCI_CMD; + off = RTE_PCI_COMMAND; cmd = 0; if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) { DLB2_LOG_ERR("[%s()] failed to write the pci command\n", @@ -468,9 +466,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } - off = DLB2_PCI_CMD; + off = RTE_PCI_COMMAND; if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) { - cmd &= ~DLB2_PCI_COMMAND_INTX_DISABLE; + cmd &= ~RTE_PCI_COMMAND_INTX_DISABLE; if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) { DLB2_LOG_ERR("[%s()] failed to write the pci command\n", __func__); diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index a055a28592..bf2b2639f4 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -32,10 +32,12 @@ extern "C" { #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */ #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */ -#define RTE_PCI_COMMAND 0x04 /* 16 bits */ /* PCI Command Register */ +#define RTE_PCI_COMMAND 0x04 /* 16 bits */ +#define RTE_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ #define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */ +#define RTE_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ /* PCI Status Register */ #define RTE_PCI_STATUS 0x06 /* 16 bits */ -- 2.41.0 </blockquote></div></div>