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<div dir="auto">Fair enough... I think that is just something we're going to have to live with.<br />
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The other solutions are either much more painful, or much more work.<br />
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If we can use header/buffer splitting that would be superior. Right now we can't use that everywhere because it isn't available everywhere.<br /></div>
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<div name="messageReplySection">On Mar 26, 2024 at 1:35 PM -0700, Stephen Hemminger <stephen@networkplumber.org>, wrote:<br />
<blockquote type="cite">On Tue, 26 Mar 2024 10:43:30 -0700<br />
Garrett D'Amore <garrett@damore.org> wrote:<br />
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<blockquote type="cite" style="border-left-color: grey; border-left-width: thin; border-left-style: solid; margin: 5px 5px;padding-left: 10px;">This had occurred to me as well. I think most hardware DMA engines can align on 32-bit boundaries. I've yet to see a device that actually requires 64-bit DMA alignment. (But I have only looked at a subset of devices, and most of the ones I have looked at are not ones that would be considered 'modern'.)<br /></blockquote>
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There maybe a PCI transaction performance penalty if not aligned.<br /></blockquote>
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