Implement the flow tables resources get operation by agent channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 13 + drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_np.c | 492 +++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 282 +++++++++++++++++++ 4 files changed, 788 insertions(+) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index e683cbd616..ea34b9229b 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1809,6 +1809,19 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) return ret; } } + + if (hw->is_pf) { + ret = zxdh_np_se_res_get_and_init(hw->dev_id, ZXDH_SE_STD_NIC_RES_TYPE); + if (ret) { + PMD_DRV_LOG(ERR, "dpp apt init failed, code:%d ", ret); + return -ret; + } + if (hw->hash_search_index >= ZXDH_HASHIDX_MAX) { + PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); + return -1; + } + } + if (zxdh_shared_data != NULL) zxdh_shared_data->np_init_done = 1; diff --git a/drivers/net/zxdh/zxdh_ethdev.h b/drivers/net/zxdh/zxdh_ethdev.h index 04b0b58c74..261acd17c3 100644 --- a/drivers/net/zxdh/zxdh_ethdev.h +++ b/drivers/net/zxdh/zxdh_ethdev.h @@ -44,6 +44,7 @@ #define ZXDH_MAX_NAME_LEN 32 #define ZXDH_SLOT_MAX 256 #define ZXDH_MAX_VF 256 +#define ZXDH_HASHIDX_MAX 6 union zxdh_virport_num { uint16_t vport; diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index fd9c7b47c9..c93f8eb0fb 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -2508,6 +2508,40 @@ zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, return msg_result; } +static uint32_t +zxdh_np_agent_channel_se_res_get(uint32_t dev_id, + uint32_t sub_type, + uint32_t opr, + uint32_t *p_rsp_buff, + uint32_t buff_size) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + ZXDH_AGENT_SE_RES_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_RES_MSG, + .sub_type = sub_type, + .oper = opr, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_SE_RES_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "agent send msg failed"); + return ZXDH_ERR; + } + + msg_result = p_rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: 0x%x", msg_result); + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -5239,6 +5273,464 @@ zxdh_np_host_init(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_get_se_buff_size(uint32_t opr) +{ + uint32_t buff_size = 0; + + switch (opr) { + case ZXDH_HASH_FUNC_BULK_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_FUNC_BULK_T); + break; + case ZXDH_HASH_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_TBL_T); + break; + case ZXDH_ERAM_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ERAM_TBL_T); + break; + case ZXDH_ACL_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ACL_TBL_T); + break; + case ZXDH_STAT_CFG_REQ: + buff_size = sizeof(ZXDH_NP_SE_STAT_CFG_T); + break; + default: + break; + } + + return buff_size; +} + +static void +zxdh_np_hash_func_bulk_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk) +{ + uint32_t index = 0; + ZXDH_APT_HASH_FUNC_RES_T *p_func_res = NULL; + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res = NULL; + + p_hash_res_init->func_num = p_func_bulk->func_num; + p_hash_res_init->bulk_num = p_func_bulk->bulk_num; + for (index = 0; index < (p_hash_res_init->func_num); index++) { + p_func_res = p_hash_res_init->func_res + index; + + p_func_res->func_id = p_func_bulk->fun[index].func_id; + p_func_res->ddr_dis = p_func_bulk->fun[index].ddr_dis; + p_func_res->zblk_num = p_func_bulk->fun[index].zblk_num; + p_func_res->zblk_bitmap = p_func_bulk->fun[index].zblk_bitmap; + } + + for (index = 0; index < (p_hash_res_init->bulk_num); index++) { + p_bulk_res = p_hash_res_init->bulk_res + index; + + p_bulk_res->func_id = p_func_bulk->bulk[index].func_id; + p_bulk_res->bulk_id = p_func_bulk->bulk[index].bulk_id; + p_bulk_res->zcell_num = p_func_bulk->bulk[index].zcell_num; + p_bulk_res->zreg_num = p_func_bulk->bulk[index].zreg_num; + p_bulk_res->ddr_baddr = p_func_bulk->bulk[index].ddr_baddr; + p_bulk_res->ddr_item_num = p_func_bulk->bulk[index].ddr_item_num; + p_bulk_res->ddr_width_mode = p_func_bulk->bulk[index].ddr_width_mode; + p_bulk_res->ddr_crc_sel = p_func_bulk->bulk[index].ddr_crc_sel; + p_bulk_res->ddr_ecc_en = p_func_bulk->bulk[index].ddr_ecc_en; + } +} + +static void +zxdh_np_hash_tbl_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl) +{ + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_tbl_res = NULL; + + p_hash_res_init->tbl_num = p_hash_tbl->tbl_num; + for (index = 0; index < (p_hash_res_init->tbl_num); index++) { + p_tbl_res = p_hash_res_init->tbl_res + index; + + p_tbl_res->sdt_no = p_hash_tbl->table[index].sdt_no; + p_tbl_res->sdt_partner = p_hash_tbl->table[index].sdt_partner; + p_tbl_res->tbl_flag = p_hash_tbl->table[index].tbl_flag; + p_tbl_res->hash_sdt.table_type = + p_hash_tbl->table[index].hash_sdt.table_type; + p_tbl_res->hash_sdt.hash_id = p_hash_tbl->table[index].hash_sdt.hash_id; + p_tbl_res->hash_sdt.hash_table_width = + p_hash_tbl->table[index].hash_sdt.hash_table_width; + p_tbl_res->hash_sdt.key_size = p_hash_tbl->table[index].hash_sdt.key_size; + p_tbl_res->hash_sdt.hash_table_id = + p_hash_tbl->table[index].hash_sdt.hash_table_id; + p_tbl_res->hash_sdt.learn_en = p_hash_tbl->table[index].hash_sdt.learn_en; + p_tbl_res->hash_sdt.keep_alive = + p_hash_tbl->table[index].hash_sdt.keep_alive; + p_tbl_res->hash_sdt.keep_alive_baddr = + p_hash_tbl->table[index].hash_sdt.keep_alive_baddr; + p_tbl_res->hash_sdt.rsp_mode = + p_hash_tbl->table[index].hash_sdt.rsp_mode; + p_tbl_res->hash_sdt.hash_clutch_en = + p_hash_tbl->table[index].hash_sdt.hash_clutch_en; + } +} + +static void +zxdh_np_eram_tbl_set(ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init, ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_eram_res = NULL; + + p_eam_res_init->tbl_num = p_eram_tbl->tbl_num; + for (index = 0; index < (p_eam_res_init->tbl_num); index++) { + p_eram_res = p_eam_res_init->eram_res + index; + + p_eram_res->sdt_no = p_eram_tbl->eram[index].sdt_no; + p_eram_res->opr_mode = p_eram_tbl->eram[index].opr_mode; + p_eram_res->rd_mode = p_eram_tbl->eram[index].rd_mode; + p_eram_res->eram_sdt.table_type = p_eram_tbl->eram[index].eram_sdt.table_type; + p_eram_res->eram_sdt.eram_mode = p_eram_tbl->eram[index].eram_sdt.eram_mode; + p_eram_res->eram_sdt.eram_base_addr = + p_eram_tbl->eram[index].eram_sdt.eram_base_addr; + p_eram_res->eram_sdt.eram_table_depth = + p_eram_tbl->eram[index].eram_sdt.eram_table_depth; + p_eram_res->eram_sdt.eram_clutch_en = + p_eram_tbl->eram[index].eram_sdt.eram_clutch_en; + } +} + +static void +zxdh_np_acl_tbl_set(ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init, ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_acl_res = NULL; + + p_acl_res_init->tbl_num = p_acl_tbl->tbl_num; + for (index = 0; index < (p_acl_tbl->tbl_num); index++) { + p_acl_res = p_acl_res_init->acl_res + index; + + p_acl_res->sdt_no = p_acl_tbl->acl[index].sdt_no; + p_acl_res->sdt_partner = p_acl_tbl->acl[index].sdt_partner; + p_acl_res->acl_res.block_num = p_acl_tbl->acl[index].acl_res.block_num; + p_acl_res->acl_res.entry_num = p_acl_tbl->acl[index].acl_res.entry_num; + p_acl_res->acl_res.pri_mode = p_acl_tbl->acl[index].acl_res.pri_mode; + memcpy(p_acl_res->acl_res.block_index, + p_acl_tbl->acl[index].acl_res.block_index, + sizeof(uint32_t) * ZXDH_ETCAM_BLOCK_NUM); + p_acl_res->acl_sdt.table_type = p_acl_tbl->acl[index].acl_sdt.table_type; + p_acl_res->acl_sdt.etcam_id = p_acl_tbl->acl[index].acl_sdt.etcam_id; + p_acl_res->acl_sdt.etcam_key_mode = p_acl_tbl->acl[index].acl_sdt.etcam_key_mode; + p_acl_res->acl_sdt.etcam_table_id = p_acl_tbl->acl[index].acl_sdt.etcam_table_id; + p_acl_res->acl_sdt.no_as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.no_as_rsp_mode; + p_acl_res->acl_sdt.as_en = p_acl_tbl->acl[index].acl_sdt.as_en; + p_acl_res->acl_sdt.as_eram_baddr = p_acl_tbl->acl[index].acl_sdt.as_eram_baddr; + p_acl_res->acl_sdt.as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.as_rsp_mode; + p_acl_res->acl_sdt.etcam_table_depth = + p_acl_tbl->acl[index].acl_sdt.etcam_table_depth; + p_acl_res->acl_sdt.etcam_clutch_en = p_acl_tbl->acl[index].acl_sdt.etcam_clutch_en; + } +} + +static void +zxdh_np_stat_cfg_set(ZXDH_APT_STAT_RES_INIT_T *p_stat_res_init, ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg) +{ + p_stat_res_init->eram_baddr = p_stat_cfg->eram_baddr; + p_stat_res_init->eram_depth = p_stat_cfg->eram_depth; + p_stat_res_init->ddr_baddr = p_stat_cfg->ddr_baddr; + p_stat_res_init->ppu_ddr_offset = p_stat_cfg->ppu_ddr_offset; +} + +static uint32_t +zxdh_np_agent_hash_func_bulk_get(uint32_t dev_id, uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_FUNC_BULK_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash func&bulk res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_func_bulk = (ZXDH_NP_SE_HASH_FUNC_BULK_T *)(p_rsp_buff + 1); + zxdh_np_hash_func_bulk_set(p_hash_res_init, p_func_bulk); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_hash_tbl_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_hash_tbl = (ZXDH_NP_SE_HASH_TBL_T *)(p_rsp_buff + 1); + zxdh_np_hash_tbl_set(p_hash_res_init, p_hash_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_eram_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ERAM_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "eram table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_eram_tbl = (ZXDH_NP_SE_ERAM_TBL_T *)(p_rsp_buff + 1); + zxdh_np_eram_tbl_set(p_eam_res_init, p_eram_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_acl_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ACL_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "acl table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_acl_tbl = (ZXDH_NP_SE_ACL_TBL_T *)(p_rsp_buff + 1); + zxdh_np_acl_tbl_set(p_acl_res_init, p_acl_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_stat_cfg_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_STAT_RES_INIT_T *p_stat_cfg_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_STAT_CFG_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "ddr table res get fail rc = 0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_stat_cfg = (ZXDH_NP_SE_STAT_CFG_T *)(p_rsp_buff + 1); + zxdh_np_stat_cfg_set(p_stat_cfg_init, p_stat_cfg); + rte_free(p_rsp_buff); + + return rc; +} + +static void * +zxdh_np_dev_get_se_res_ptr(uint32_t dev_id, uint32_t type) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (type == ZXDH_SE_STD_NIC_RES_TYPE) + return (void *)&p_dev_info->dev_apt_se_tbl_res.std_nic_res; + else + return (void *)&p_dev_info->dev_apt_se_tbl_res.offload_res; +} + +static uint32_t +zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_res); + + if (p_se_res->valid) { + PMD_DRV_LOG(INFO, "dev_id [0x%x] res_type [%u] status ready", dev_id, type); + return ZXDH_OK; + } + + hash_res.func_res = p_se_res->hash_func; + hash_res.bulk_res = p_se_res->hash_bulk; + hash_res.tbl_res = p_se_res->hash_tbl; + rc = zxdh_np_agent_hash_func_bulk_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_func_bulk_get"); + + rc = zxdh_np_agent_hash_tbl_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_tbl_get"); + p_se_res->hash_func_num = hash_res.func_num; + p_se_res->hash_bulk_num = hash_res.bulk_num; + p_se_res->hash_tbl_num = hash_res.tbl_num; + + eram_res.eram_res = p_se_res->eram_tbl; + rc = zxdh_np_agent_eram_tbl_get(dev_id, type, &eram_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_eram_tbl_get"); + p_se_res->eram_num = eram_res.tbl_num; + + acl_res.acl_res = p_se_res->acl_tbl; + rc = zxdh_np_agent_acl_tbl_get(dev_id, type, &acl_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_acl_tbl_get"); + p_se_res->acl_num = acl_res.tbl_num; + + rc = zxdh_np_agent_stat_cfg_get(dev_id, type, &p_se_res->stat_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_stat_cfg_get"); + + p_se_res->valid = 1; + return rc; +} + +uint32_t +zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_agent_se_res_get(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); + PMD_DRV_LOG(DEBUG, "se res get success."); + + return rc; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index d4a940b038..b204889c9a 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -130,6 +130,12 @@ #define ZXDH_LISTSTACK_INVALID_INDEX (0) #define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) +#define ZXDH_HASH_FUNC_MAX_NUM (4) +#define ZXDH_HASH_BULK_MAX_NUM (32) +#define ZXDH_HASH_TABLE_MAX_NUM (38) +#define ZXDH_ERAM_MAX_NUM (60) +#define ZXDH_ETCAM_MAX_NUM (8) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -521,6 +527,33 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef enum zxdh_hash_srh_mode { + ZXDH_HASH_SRH_MODE_SOFT = 1, + ZXDH_HASH_SRH_MODE_HDW = 2, +} ZXDH_HASH_SRH_MODE; + +typedef struct zxdh_hash_entry { + uint8_t *p_key; + uint8_t *p_rst; +} ZXDH_HASH_ENTRY; + +typedef struct zxdh_acl_entry_ex_t { + uint32_t idx_val; + ZXDH_D_HEAD idx_list; + uint32_t pri; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_ACL_ENTRY_EX_T; + +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_SET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_GET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ERAM_SET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_ERAM_GET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_SET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_GET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef int32_t (*ZXDH_KEY_CMP_FUNC)(void *p_new_key, void *p_old_key, uint32_t key_len); + typedef struct zxdh_sdt_tbl_eram_t { uint32_t table_type; uint32_t eram_mode; @@ -555,6 +588,113 @@ typedef struct zxdh_sdt_tbl_hash_t { uint32_t hash_clutch_en; } ZXDH_SDT_TBL_HASH_T; +typedef enum zxdh_hash_ddr_width_mode_e { + ZXDH_DDR_WIDTH_INVALID = 0, + ZXDH_DDR_WIDTH_256b, + ZXDH_DDR_WIDTH_512b, +} ZXDH_HASH_DDR_WIDTH_MODE; + +typedef struct zxdh_apt_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_APT_ACL_RES_T; + +typedef struct zxdh_apt_hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + ZXDH_HASH_DDR_WIDTH_MODE ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_APT_HASH_BULK_RES_T; + +typedef struct zxdh_apt_hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_APT_HASH_FUNC_RES_T; + +typedef struct zxdh_apt_eram_table_t { + uint32_t sdt_no; + ZXDH_SDT_TBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_APT_ERAM_TABLE_T; + +typedef struct zxdh_apt_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_ETCAM_T acl_sdt; + ZXDH_APT_ACL_RES_T acl_res; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_APT_ACL_TABLE_T; + +typedef struct zxdh_apt_hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_HASH_T hash_sdt; + uint32_t tbl_flag; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_APT_HASH_TABLE_T; + +typedef struct zxdh_apt_eram_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ERAM_TABLE_T *eram_res; +} ZXDH_APT_ERAM_RES_INIT_T; + +typedef struct zxdh_apt_hash_res_init_t { + uint32_t func_num; + uint32_t bulk_num; + uint32_t tbl_num; + ZXDH_APT_HASH_FUNC_RES_T *func_res; + ZXDH_APT_HASH_BULK_RES_T *bulk_res; + ZXDH_APT_HASH_TABLE_T *tbl_res; +} ZXDH_APT_HASH_RES_INIT_T; + +typedef struct zxdh_apt_acl_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ACL_TABLE_T *acl_res; +} ZXDH_APT_ACL_RES_INIT_T; + +typedef struct zxdh_apt_stat_res_init_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_APT_STAT_RES_INIT_T; + +typedef struct zxdh_apt_se_res_t { + uint32_t valid; + uint32_t hash_func_num; + uint32_t hash_bulk_num; + uint32_t hash_tbl_num; + uint32_t eram_num; + uint32_t acl_num; + uint32_t lpm_num; + uint32_t ddr_num; + ZXDH_APT_HASH_FUNC_RES_T hash_func[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_APT_HASH_BULK_RES_T hash_bulk[ZXDH_HASH_BULK_MAX_NUM]; + ZXDH_APT_HASH_TABLE_T hash_tbl[ZXDH_HASH_TABLE_MAX_NUM]; + ZXDH_APT_ERAM_TABLE_T eram_tbl[ZXDH_ERAM_MAX_NUM]; + ZXDH_APT_ACL_TABLE_T acl_tbl[ZXDH_ETCAM_MAX_NUM]; + ZXDH_APT_STAT_RES_INIT_T stat_cfg; +} ZXDH_APT_SE_RES_T; + +typedef struct zxdh_dev_apt_se_tbl_res_t { + ZXDH_APT_SE_RES_T std_nic_res; + ZXDH_APT_SE_RES_T offload_res; +} ZXDH_DEV_APT_SE_TBL_RES_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; @@ -596,6 +736,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -954,6 +1095,29 @@ typedef enum zxdh_msg_dtb_oper_e { ZXDH_QUEUE_RELEASE = 1, } ZXDH_MSG_DTB_OPER_E; +typedef enum zxdh_se_res_oper_e { + ZXDH_HASH_FUNC_BULK_REQ = 0, + ZXDH_HASH_TBL_REQ = 1, + ZXDH_ERAM_TBL_REQ = 2, + ZXDH_ACL_TBL_REQ = 3, + ZXDH_LPM_TBL_REQ = 4, + ZXDH_DDR_TBL_REQ = 5, + ZXDH_STAT_CFG_REQ = 6, + ZXDH_RES_REQ_MAX +} ZXDH_MSG_SE_RES_OPER_E; + +typedef enum zxdh_agent_msg_res_e { + ZXDH_RES_STD_NIC_MSG = 0, + ZXDH_RES_OFFLOAD_MSG, + ZXDH_RES_MAX_MSG +} MSG_RES_TYPE_E; + +typedef enum zxdh_se_res_type_e { + ZXDH_SE_STD_NIC_RES_TYPE = 0, + ZXDH_SE_NON_STD_NIC_RES_TYPE = 1, + ZXDH_SE_RES_TYPE_BUTT +} ZXDH_SE_RES_TYPE_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -1178,6 +1342,123 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { uint32_t queue_id; } ZXDH_AGENT_CHANNEL_DTB_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_se_res_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t sub_type; + uint8_t oper; +} ZXDH_AGENT_SE_RES_MSG_T; + +typedef struct __rte_aligned(2) sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_NP_SDTTBL_ERAM_T; + +typedef struct __rte_aligned(2) sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_NP_SDTTBL_HASH_T; + +typedef struct __rte_aligned(2) sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_NP_SDTTBL_ETCAM_T; + +typedef struct __rte_aligned(2) hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_HASH_T hash_sdt; + uint32_t tbl_flag; +} ZXDH_NP_HASH_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_eram_table_t { + uint32_t sdt_no; + ZXDH_NP_SDTTBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; +} ZXDH_NP_ERAM_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_NP_ACL_RES_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_ETCAM_T acl_sdt; + ZXDH_NP_ACL_RES_T acl_res; +} ZXDH_NP_ACL_TABLE_T; + +typedef struct __rte_aligned(2) hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_NP_HASH_FUNC_RES_T; + +typedef struct __rte_aligned(2) hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_NP_HASH_BULK_RES_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_func_bulk_t { + uint32_t func_num; + uint32_t bulk_num; + ZXDH_NP_HASH_FUNC_RES_T fun[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_NP_HASH_BULK_RES_T bulk[ZXDH_HASH_BULK_MAX_NUM]; +} ZXDH_NP_SE_HASH_FUNC_BULK_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_tbl_t { + uint32_t tbl_num; + ZXDH_NP_HASH_TABLE_T table[ZXDH_HASH_TABLE_MAX_NUM]; +} ZXDH_NP_SE_HASH_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_eram_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ERAM_TABLE_T eram[ZXDH_ERAM_MAX_NUM]; +} ZXDH_NP_SE_ERAM_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_acl_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ACL_TABLE_T acl[ZXDH_ETCAM_MAX_NUM]; +} ZXDH_NP_SE_ACL_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_NP_SE_STAT_CFG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1213,5 +1494,6 @@ uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t drop_flag, uint32_t plcr_en, uint32_t profile_id); +uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); #endif /* ZXDH_NP_H */ -- 2.27.0