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<p class="MsoNormal"><span lang="EN-GB">Please find below NVIDIA roadmap for 25.07 release:</span> <o:p></o:p></p>
<p class="MsoNormal"> <o:p></o:p></p>
<p class="MsoNormal"><span lang="EN-GB">EAL change</span> <o:p></o:p></p>
<p class="MsoNormal"><span lang="EN-GB">=============</span> <o:p></o:p></p>
<p class="MsoNormal"><span lang="EN-GB">Improve PCI device string comparisons by using bus-specific parsing functions.</span> <o:p></o:p></p>
<p class="MsoNormal"><span lang="EN-GB">Ensure consistent handling of PCI device numbers, regardless of the format used by comparing the parsed PCI
<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-GB">address instances instead of the string representations.
</span> <o:p></o:p></p>
<p class="MsoNormal"> <o:p></o:p></p>
<p class="MsoNormal"><span lang="EN-US">Net/mlx5 PMD updates</span><span lang="EN-US" style="font-family:"Arial",sans-serif"> </span><span style="font-family:"Arial",sans-serif"> </span> <o:p></o:p></p>
<p class="MsoNormal"><span lang="EN-US">=====================</span><span lang="EN-US" style="font-family:"Arial",sans-serif"> </span><span style="font-family:"Arial",sans-serif"> </span> <o:p></o:p></p>
<ol style="margin-top:0cm" start="1" type="1">
<li class="MsoNormal" style="mso-list:l5 level1 lfo4"><span lang="EN-US">Tx datapath optimization</span> <o:p></o:p></li></ol>
<p class="MsoNormal" style="text-indent:36.0pt"><span lang="EN-US">Optimize Tx datapath performance by changing Tx inner buffers allocation and alignment in memory.</span> <o:p></o:p></p>
<ol style="margin-top:0cm" start="2" type="1">
<li class="MsoNormal" style="mso-list:l1 level1 lfo5"><span lang="EN-US">Memory statistics visibility for debugging</span> <o:p></o:p></li></ol>
<p class="MsoNormal"><span lang="EN-US"> Adding new xstats counters for debugging memory usage and allocations.</span> <o:p></o:p></p>
<ol style="margin-top:0cm" start="3" type="1">
<li class="MsoNormal" style="mso-list:l9 level1 lfo6"><span lang="EN-US">Support for legacy rte_flow</span><span lang="EN-US" style="font-family:"Arial",sans-serif"> </span><span lang="EN-US">(non-template) on top of the async hardware mechanism (HWS)
</span><o:p></o:p></li></ol>
<p class="MsoNormal" style="margin-left:36.0pt"><span lang="EN-US">has been added as a beta feature, serving as a preview for future NICs (e.g., ConnectX-9+),
<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:36.0pt"><span lang="EN-US">where legacy rte_flow will no longer be supported,
</span><o:p></o:p></p>
<p class="MsoNormal" style="margin-left:36.0pt"><span lang="EN-US">and will be exchanged with the [already available] template async interface. </span> <o:p></o:p></p>
<p class="MsoNormal" style="margin-left:36.0pt"><span lang="EN-US">While this mode is compatible with older NICs (prior to ConnectX-9),
<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:36.0pt"><span lang="EN-US">it is not recommended since existing legacy mode delivers better performance.
<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:36.0pt"><span lang="EN-US">Developers are strongly encouraged to transition to the template API for both
<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:36.0pt"><span lang="EN-US">superior performance and access to an enhanced feature set.</span> <o:p></o:p></p>
<ol style="margin-top:0cm" start="4" type="1">
<li class="MsoNormal" style="mso-list:l7 level1 lfo7"><span lang="EN-US">Handle SF/VF representor removal in DPDK (supported with ConnectX-6DX and above)</span> <o:p></o:p></li></ol>
<p class="MsoNormal" style="text-indent:36.0pt"><span lang="EN-US">Listen to the kernel events and remove needed SFs/VFs representors.</span> <o:p></o:p></p>
<ol style="margin-top:0cm" start="5" type="1">
<li class="MsoNormal" style="mso-list:l6 level1 lfo8"><span lang="EN-US">Cross Numa support</span> <o:p></o:p></li></ol>
<p class="MsoNormal" style="text-indent:36.0pt"><span lang="EN-US">Enable fallback to any socket to support cross NUMA memory allocations during initialization.</span> <o:p></o:p></p>
<ol style="margin-top:0cm" start="6" type="1">
<li class="MsoNormal" style="mso-list:l3 level1 lfo9"><span lang="EN-US">Support matching on IPv6 frag extension header with rte_flow template API.</span> <o:p></o:p></li></ol>
<ol style="margin-top:0cm" start="7" type="1">
<li class="MsoNormal" style="mso-list:l10 level1 lfo10"><span lang="EN-US">Support RTE_FLOW_ACTION_TYPE_COUNT on group 0 (root) in rte_flow template API.</span> <o:p></o:p></li></ol>
<ol style="margin-top:0cm" start="8" type="1">
<li class="MsoNormal" style="mso-list:l0 level1 lfo11"><span lang="EN-US">Support IP-in-IP matching in rte_flow template API.</span> <o:p></o:p></li></ol>
<p class="MsoNormal"> <o:p></o:p></p>
<p class="MsoNormal">Doc <o:p></o:p></p>
<p class="MsoNormal">======= <o:p></o:p></p>
<p class="MsoNormal"><span lang="EN-US">Updated mlx5 documentation with feature description and usage examples.</span> <o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span lang="en-IL"><o:p> </o:p></span></p>
<div>
<p class="MsoNormal"><span lang="EN-US" style="mso-ligatures:standardcontextual;mso-fareast-language:#2000">Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-ligatures:standardcontextual;mso-fareast-language:#2000">Maayan Kashani<o:p></o:p></span></p>
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