<div dir="ltr">Okay, I'll make a ticket for us to look at this again and raise it at the CI meeting this morning. Thanks for the heads up.</div><br><div class="gmail_quote gmail_quote_container"><div dir="ltr" class="gmail_attr">On Thu, May 15, 2025 at 8:59 AM David Marchand <<a href="mailto:david.marchand@redhat.com">david.marchand@redhat.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">On Tue, Apr 2, 2024 at 2:46 AM Stephen Hemminger<br>
<<a href="mailto:stephen@networkplumber.org" target="_blank">stephen@networkplumber.org</a>> wrote:<br>
><br>
> On Mon, 1 Apr 2024 18:26:44 -0400<br>
> Patrick Robb <<a href="mailto:probb@iol.unh.edu" target="_blank">probb@iol.unh.edu</a>> wrote:<br>
><br>
> > Another idea - maybe multiple timestamps are gathered from different<br>
> > CPU registers during the same test, and they are misaligned for that<br>
> > reason. Maybe we can try reducing the cores for each unit test to 1<br>
> > and checking whether the issue persists.<br>
><br>
> TSC is expected to be sync'd between cores. But of course packets can<br>
> arrive out of order on different cores.<br>
<br>
Just a note that there was one more occurence of this false positive today.<br>
<a href="https://lab.dpdk.org/results/dashboard/patchsets/33170/" rel="noreferrer" target="_blank">https://lab.dpdk.org/results/dashboard/patchsets/33170/</a><br>
<br>
<br>
-- <br>
David Marchand<br>
<br>
</blockquote></div>