<div dir="auto">Why is this needed? Need some documentation. DPDK needs less not more nerd knobs </div><br><div class="gmail_quote gmail_quote_container"><div dir="ltr" class="gmail_attr">On Mon, Jun 23, 2025, 14:35 Bing Zhao <<a href="mailto:bingz@nvidia.com">bingz@nvidia.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">With this commit, a new device argument is introduced to control<br>
the memory allocation for Tx queues.<br>
<br>
By default, 'txq_consec_mem' is 1 to let all the Tx queues use a<br>
consecutive memory area and a single MR.<br>
<br>
Signed-off-by: Bing Zhao <<a href="mailto:bingz@nvidia.com" target="_blank" rel="noreferrer">bingz@nvidia.com</a>><br>
---<br>
drivers/net/mlx5/mlx5.c | 14 ++++++++++++++<br>
drivers/net/mlx5/mlx5.h | 1 +<br>
2 files changed, 15 insertions(+)<br>
<br>
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c<br>
index b4bd43aae2..f5beebd2fd 100644<br>
--- a/drivers/net/mlx5/mlx5.c<br>
+++ b/drivers/net/mlx5/mlx5.c<br>
@@ -185,6 +185,9 @@<br>
/* Device parameter to control representor matching in ingress/egress flows with HWS. */<br>
#define MLX5_REPR_MATCHING_EN "repr_matching_en"<br>
<br>
+/* Using consecutive memory address and single MR for all Tx queues. */<br>
+#define MLX5_TXQ_CONSEC_MEM "txq_consec_mem"<br>
+<br>
/* Shared memory between primary and secondary processes. */<br>
struct mlx5_shared_data *mlx5_shared_data;<br>
<br>
@@ -1447,6 +1450,8 @@ mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque)<br>
config->cnt_svc.cycle_time = tmp;<br>
} else if (strcmp(MLX5_REPR_MATCHING_EN, key) == 0) {<br>
config->repr_matching = !!tmp;<br>
+ } else if (strcmp(MLX5_TXQ_CONSEC_MEM, key) == 0) {<br>
+ config->txq_consec_mem = !!tmp;<br>
}<br>
return 0;<br>
}<br>
@@ -1486,6 +1491,7 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,<br>
MLX5_HWS_CNT_SERVICE_CORE,<br>
MLX5_HWS_CNT_CYCLE_TIME,<br>
MLX5_REPR_MATCHING_EN,<br>
+ MLX5_TXQ_CONSEC_MEM,<br>
NULL,<br>
};<br>
int ret = 0;<br>
@@ -1501,6 +1507,7 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,<br>
config->cnt_svc.cycle_time = MLX5_CNT_SVC_CYCLE_TIME_DEFAULT;<br>
config->cnt_svc.service_core = rte_get_main_lcore();<br>
config->repr_matching = 1;<br>
+ config->txq_consec_mem = 1;<br>
if (mkvlist != NULL) {<br>
/* Process parameters. */<br>
ret = mlx5_kvargs_process(mkvlist, params,<br>
@@ -1584,6 +1591,7 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,<br>
config->allow_duplicate_pattern);<br>
DRV_LOG(DEBUG, "\"fdb_def_rule_en\" is %u.", config->fdb_def_rule);<br>
DRV_LOG(DEBUG, "\"repr_matching_en\" is %u.", config->repr_matching);<br>
+ DRV_LOG(DEBUG, "\"txq_consec_mem\" is %u.", config->txq_consec_mem);<br>
return 0;<br>
}<br>
<br>
@@ -3150,6 +3158,12 @@ mlx5_probe_again_args_validate(struct mlx5_common_device *cdev,<br>
sh->ibdev_name);<br>
goto error;<br>
}<br>
+ if (sh->config.txq_consec_mem ^ config->txq_consec_mem) {<br>
+ DRV_LOG(ERR, "\"txq_consec_mem\" "<br>
+ "configuration mismatch for shared %s context.",<br>
+ sh->ibdev_name);<br>
+ goto error;<br>
+ }<br>
mlx5_free(config);<br>
return 0;<br>
error:<br>
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h<br>
index 5695d0f54a..4e0287cbc0 100644<br>
--- a/drivers/net/mlx5/mlx5.h<br>
+++ b/drivers/net/mlx5/mlx5.h<br>
@@ -393,6 +393,7 @@ struct mlx5_sh_config {<br>
/* Allow/Prevent the duplicate rules pattern. */<br>
uint32_t fdb_def_rule:1; /* Create FDB default jump rule */<br>
uint32_t repr_matching:1; /* Enable implicit vport matching in HWS FDB. */<br>
+ uint32_t txq_consec_mem:1; /**/<br>
};<br>
<br>
/* Structure for VF VLAN workaround. */<br>
-- <br>
2.34.1<br>
<br>
</blockquote></div>