<div dir="auto"><div><br><br><div class="gmail_quote gmail_quote_container"><div dir="ltr" class="gmail_attr">On Tue, 1 Jul 2025, 20:21 , <<a href="mailto:uk7b@foxmail.com">uk7b@foxmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: Sun Yuechi <<a href="mailto:sunyuechi@iscas.ac.cn" target="_blank" rel="noreferrer">sunyuechi@iscas.ac.cn</a>><br>
<br>
This patch is derived from "config/riscv: detect presence of Zbc<br>
extension with modifications".<br>
<br>
The RISC-V C api defines architecture extension test macros<br>
These let us detect whether the V extension is supported on the<br>
compiler and -march we're building with. The C api also defines V<br>
intrinsics we can use rather than inline assembly on newer versions of<br>
GCC (14.1.0+) and Clang (18.1.0+).<br>
<br>
If the V extension and intrinsics are both present and we can detect<br>
the V extension at runtime, we define a flag, RTE_RISCV_FEATURE_V.<br>
<br>
Signed-off-by: Sun Yuechi <<a href="mailto:sunyuechi@iscas.ac.cn" target="_blank" rel="noreferrer">sunyuechi@iscas.ac.cn</a>><br></blockquote></div></div><div dir="auto">Reviewed-by: Stanisław Kardach <<a href="mailto:stanislaw.kardach@gmail.com">stanislaw.kardach@gmail.com</a>></div><div dir="auto"><div class="gmail_quote gmail_quote_container"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
---<br>
.mailmap | 1 +<br>
config/riscv/meson.build | 25 +++++++++++++++++++++++++<br>
lib/eal/riscv/include/rte_vect.h | 4 ++++<br>
3 files changed, 30 insertions(+)<br>
<br>
diff --git a/.mailmap b/.mailmap<br>
index 8483d96ec5..21f5d7fb5e 100644<br>
--- a/.mailmap<br>
+++ b/.mailmap<br>
@@ -1513,6 +1513,7 @@ Sunil Kumar Kori <<a href="mailto:skori@marvell.com" target="_blank" rel="noreferrer">skori@marvell.com</a>> <<a href="mailto:skori@mavell.com" target="_blank" rel="noreferrer">skori@mavell.com</a>> <<a href="mailto:sunil.kori@nxp.com" target="_blank" rel="noreferrer">sunil.kori@nxp.com</a>><br>
Sunil Pai G <<a href="mailto:sunil.pai.g@intel.com" target="_blank" rel="noreferrer">sunil.pai.g@intel.com</a>><br>
Sunil Uttarwar <<a href="mailto:sunilprakashrao.uttarwar@amd.com" target="_blank" rel="noreferrer">sunilprakashrao.uttarwar@amd.com</a>><br>
Sun Jiajia <<a href="mailto:sunx.jiajia@intel.com" target="_blank" rel="noreferrer">sunx.jiajia@intel.com</a>><br>
+Sun Yuechi <<a href="mailto:sunyuechi@iscas.ac.cn" target="_blank" rel="noreferrer">sunyuechi@iscas.ac.cn</a>> <<a href="mailto:uk7b@foxmail.com" target="_blank" rel="noreferrer">uk7b@foxmail.com</a>><br>
Sunyang Wu <<a href="mailto:sunyang.wu@jaguarmicro.com" target="_blank" rel="noreferrer">sunyang.wu@jaguarmicro.com</a>><br>
Surabhi Boob <<a href="mailto:surabhi.boob@intel.com" target="_blank" rel="noreferrer">surabhi.boob@intel.com</a>><br>
Suyang Ju <<a href="mailto:sju@paloaltonetworks.com" target="_blank" rel="noreferrer">sju@paloaltonetworks.com</a>><br>
diff --git a/config/riscv/meson.build b/config/riscv/meson.build<br>
index 7562c6cb99..e3694cf2e6 100644<br>
--- a/config/riscv/meson.build<br>
+++ b/config/riscv/meson.build<br>
@@ -119,6 +119,31 @@ foreach flag: arch_config['machine_args']<br>
endif<br>
endforeach<br>
<br>
+# check if we can do buildtime detection of extensions supported by the target<br>
+riscv_extension_macros = false<br>
+if (cc.get_define('__riscv_arch_test', args: machine_args) == '1')<br>
+ message('Detected architecture extension test macros')<br>
+ riscv_extension_macros = true<br>
+else<br>
+ warning('RISC-V architecture extension test macros not available. Build-time detection of extensions not possible')<br>
+endif<br>
+<br>
+# detect extensions<br>
+# Requires intrinsics available in GCC 14.1.0+ and Clang 18.1.0+<br>
+if (riscv_extension_macros and<br>
+ (cc.get_define('__riscv_vector', args: machine_args) != ''))<br>
+ if ((cc.get_id() == 'gcc' and cc.version().version_compare('>=14.1.0'))<br>
+ or (cc.get_id() == 'clang' and cc.version().version_compare('>=18.1.0')))<br>
+ if (cc.compiles('''#include <riscv_vector.h><br>
+ int main(void) { size_t vl = __riscv_vsetvl_e32m1(1); }''', args: machine_args))<br>
+ message('Compiling with the V extension')<br>
+ machine_args += ['-DRTE_RISCV_FEATURE_V']<br>
+ endif<br>
+ else<br>
+ warning('Detected V extension but cannot use because intrinsics are not available (present in GCC 14.1.0+ and Clang 18.1.0+)')<br>
+ endif<br>
+endif<br>
+<br>
# apply flags<br>
foreach flag: dpdk_flags<br>
if flag.length() > 0<br>
diff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h<br>
index 6df10fa8ee..a4357e266a 100644<br>
--- a/lib/eal/riscv/include/rte_vect.h<br>
+++ b/lib/eal/riscv/include/rte_vect.h<br>
@@ -11,6 +11,10 @@<br>
#include "generic/rte_vect.h"<br>
#include "rte_common.h"<br>
<br>
+#ifdef RTE_RISCV_FEATURE_V<br>
+#include <riscv_vector.h><br>
+#endif<br>
+<br>
#ifdef __cplusplus<br>
extern "C" {<br>
#endif<br>
-- <br>
2.50.0<br>
<br>
</blockquote></div></div></div>