[dpdk-stable] [dpdk-dev] [PATCH] net/cxgbe: update Chelsio T5/T6 NIC device ids

Rahul Lakkireddy rahul.lakkireddy at chelsio.com
Thu May 9 12:03:33 CEST 2019


On Thursday, May 05/09/19, 2019 at 14:29:05 +0530, Kevin Traynor wrote:
> On 19/04/2019 10:22, Rahul Lakkireddy wrote:
> > Fixes: 04868e5bfddd ("net/cxgbe: add support to run Chelsio T6 cards")
> > Cc: stable at dpdk.org
> > 
> 
> Hi Rahul,
> 
> Which stable release(s) is this change requested for? Have you tested
> these devices on those branches to ensure they work with the cxgbe pmd
> on those branches?
> 
> Kevin.

Hi Kevin,

Please target 18.11 and 19.02 branches. All these devices work fine
in these branches.

Thanks,
Rahul

> 
> > Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy at chelsio.com>
> > ---
> >  drivers/net/cxgbe/base/t4_pci_id_tbl.h | 52 +++++++++++++++++++++++++-
> >  1 file changed, 51 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/net/cxgbe/base/t4_pci_id_tbl.h b/drivers/net/cxgbe/base/t4_pci_id_tbl.h
> > index 5f5cbe048..f5f027a2e 100644
> > --- a/drivers/net/cxgbe/base/t4_pci_id_tbl.h
> > +++ b/drivers/net/cxgbe/base/t4_pci_id_tbl.h
> > @@ -1,5 +1,5 @@
> >  /* SPDX-License-Identifier: BSD-3-Clause
> > - * Copyright(c) 2014-2018 Chelsio Communications.
> > + * Copyright(c) 2014-2019 Chelsio Communications.
> >   * All rights reserved.
> >   */
> >  
> > @@ -103,6 +103,12 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
> >  	CH_PCI_ID_TABLE_FENTRY(0x5013),	/* T580-chr */
> >  	CH_PCI_ID_TABLE_FENTRY(0x5014),	/* T580-so */
> >  	CH_PCI_ID_TABLE_FENTRY(0x5015),	/* T502-bt */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5016),	/* T580-OCP-SO */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5017),	/* T520-OCP-SO */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5018),	/* T540-BT */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5019),	/* T540-LP-BT */
> > +	CH_PCI_ID_TABLE_FENTRY(0x501a),	/* T540-SO-BT */
> > +	CH_PCI_ID_TABLE_FENTRY(0x501b),	/* T540-SO-CR */
> >  	CH_PCI_ID_TABLE_FENTRY(0x5080),	/* Custom T540-cr */
> >  	CH_PCI_ID_TABLE_FENTRY(0x5081),	/* Custom T540-LL-cr */
> >  	CH_PCI_ID_TABLE_FENTRY(0x5082),	/* Custom T504-cr */
> > @@ -116,19 +122,63 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
> >  	CH_PCI_ID_TABLE_FENTRY(0x5090), /* Custom T540-CR */
> >  	CH_PCI_ID_TABLE_FENTRY(0x5091), /* Custom T522-CR */
> >  	CH_PCI_ID_TABLE_FENTRY(0x5092), /* Custom T520-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5093),	/* Custom T580-LP-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5094),	/* Custom T540-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5095),	/* Custom T540-CR-SO */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5096), /* Custom T580-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5097), /* Custom T520-KR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5098), /* Custom 2x40G QSFP */
> > +	CH_PCI_ID_TABLE_FENTRY(0x5099), /* Custom 2x40G QSFP */
> > +	CH_PCI_ID_TABLE_FENTRY(0x509A), /* Custom T520-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x509B), /* Custom T540-CR LOM */
> > +	CH_PCI_ID_TABLE_FENTRY(0x509c), /* Custom T520-CR SFP+ LOM */
> > +	CH_PCI_ID_TABLE_FENTRY(0x509d), /* Custom T540-CR SFP+ */
> > +	CH_PCI_ID_TABLE_FENTRY(0x509e), /* Custom T520-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x509f), /* Custom T540-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50a0), /* Custom T540-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50a1), /* Custom T540-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50a2), /* Custom T580-KR4 */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50a3), /* Custom T580-KR4 */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50a4), /* Custom 2x T540-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50a5), /* Custom T522-BT */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50a6), /* Custom T522-BT-SO */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50a7), /* Custom T580-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50a8), /* Custom T580-KR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50a9), /* Custom T580-KR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50aa), /* Custom T580-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50ab), /* Custom T520-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50ac), /* Custom T540-BT */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50ad), /* Custom T520-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50ae), /* Custom T540-XL-SO */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50af), /* Custom T580-KR-SO */
> > +	CH_PCI_ID_TABLE_FENTRY(0x50b0), /* Custom T520-CR-LOM */
> >  
> >  	/* T6 adapter */
> >  	CH_PCI_ID_TABLE_FENTRY(0x6001), /* T6225-CR */
> >  	CH_PCI_ID_TABLE_FENTRY(0x6002), /* T6225-SO-CR */
> >  	CH_PCI_ID_TABLE_FENTRY(0x6003), /* T6425-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6004),	/* T6425-SO-CR */
> >  	CH_PCI_ID_TABLE_FENTRY(0x6005), /* T6225-OCP */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6006),	/* T62100-OCP-SO */
> >  	CH_PCI_ID_TABLE_FENTRY(0x6007), /* T62100-LP-CR	*/
> >  	CH_PCI_ID_TABLE_FENTRY(0x6008), /* T62100-SO-CR	*/
> > +	CH_PCI_ID_TABLE_FENTRY(0x6009),	/* T6210-BT */
> >  	CH_PCI_ID_TABLE_FENTRY(0x600d), /* T62100-CR */
> >  	CH_PCI_ID_TABLE_FENTRY(0x6011), /* T6225-LL-CR */
> >  	CH_PCI_ID_TABLE_FENTRY(0x6014), /* T61100-OCP-SO */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6015),	/* T6201-BT */
> >  	CH_PCI_ID_TABLE_FENTRY(0x6080), /* Custom T6225-CR SFP28 */
> >  	CH_PCI_ID_TABLE_FENTRY(0x6081), /* Custom T62100-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6082),	/* Custom T6225-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6083),	/* Custom T62100-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6084),	/* Custom T64100-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6085),	/* Custom T6240-SO */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6086),	/* Custom T6225-SO-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6087),	/* Custom T6225-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6088),	/* Custom T62100-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x6089),	/* Custom T62100-KR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x608a),	/* Custom T62100-CR */
> > +	CH_PCI_ID_TABLE_FENTRY(0x608b),	/* Custom T6225-CR */
> >  CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
> >  
> >  #endif /* CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN */
> > 
> 


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