patch 'net/hns3: fix VF multiple count on one reset' has been queued to stable release 23.11.1

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 23.11.1

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 03/31/24. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=48d9241bbdfb813302c12f057b0d79d557856010

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 48d9241bbdfb813302c12f057b0d79d557856010 Mon Sep 17 00:00:00 2001
From: Dengdui Huang <huangdengdui at huawei.com>
Date: Fri, 8 Dec 2023 15:44:14 +0800
Subject: [PATCH] net/hns3: fix VF multiple count on one reset
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 072a07a9dcbd604b1983bf2cb266d3dd4dc89824 ]

There are two ways for the hns3 VF driver to know reset event, namely,
interrupt task and periodic detection task. For the latter, the real
reset process will delay several microseconds to execute. Both tasks
cause the count to increase by 1.

However, the periodic detection task also detects a reset event A
after interrupt task receive a reset event A. As a result, the reset
count will be double.

So this patch adds the comparison of reset level for VF in case of the
multiple reset count.

Fixes: a5475d61fa34 ("net/hns3: support VF")

Signed-off-by: Dengdui Huang <huangdengdui at huawei.com>
Signed-off-by: Jie Hai <haijie1 at huawei.com>
---
 drivers/net/hns3/hns3_ethdev_vf.c | 44 ++++++++++++++++++++-----------
 1 file changed, 29 insertions(+), 15 deletions(-)

diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c
index f5a7a2b1f4..83d3d66005 100644
--- a/drivers/net/hns3/hns3_ethdev_vf.c
+++ b/drivers/net/hns3/hns3_ethdev_vf.c
@@ -569,13 +569,8 @@ hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 		val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 		hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 		val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
-		if (clearval) {
-			hw->reset.stats.global_cnt++;
-			hns3_warn(hw, "Global reset detected, clear reset status");
-		} else {
-			hns3_schedule_delayed_reset(hns);
-			hns3_warn(hw, "Global reset detected, don't clear reset status");
-		}
+		hw->reset.stats.global_cnt++;
+		hns3_warn(hw, "Global reset detected, clear reset status");

 		ret = HNS3VF_VECTOR0_EVENT_RST;
 		goto out;
@@ -590,9 +585,9 @@ hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)

 	val = 0;
 	ret = HNS3VF_VECTOR0_EVENT_OTHER;
+
 out:
-	if (clearval)
-		*clearval = val;
+	*clearval = val;
 	return ret;
 }

@@ -1731,11 +1726,25 @@ is_vf_reset_done(struct hns3_hw *hw)
 	return true;
 }

+static enum hns3_reset_level
+hns3vf_detect_reset_event(struct hns3_hw *hw)
+{
+	enum hns3_reset_level reset = HNS3_NONE_RESET;
+	uint32_t cmdq_stat_reg;
+
+	cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
+	if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg)
+		reset = HNS3_VF_RESET;
+
+	return reset;
+}
+
 bool
 hns3vf_is_reset_pending(struct hns3_adapter *hns)
 {
+	enum hns3_reset_level last_req;
 	struct hns3_hw *hw = &hns->hw;
-	enum hns3_reset_level reset;
+	enum hns3_reset_level new_req;

 	/*
 	 * According to the protocol of PCIe, FLR to a PF device resets the PF
@@ -1758,13 +1767,18 @@ hns3vf_is_reset_pending(struct hns3_adapter *hns)
 	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 		return false;

-	hns3vf_check_event_cause(hns, NULL);
-	reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
-	if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
-	    hw->reset.level < reset) {
-		hns3_warn(hw, "High level reset %d is pending", reset);
+	new_req = hns3vf_detect_reset_event(hw);
+	if (new_req == HNS3_NONE_RESET)
+		return false;
+
+	last_req = hns3vf_get_reset_level(hw, &hw->reset.pending);
+	if (last_req == HNS3_NONE_RESET || last_req < new_req) {
+		__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+		hns3_schedule_delayed_reset(hns);
+		hns3_warn(hw, "High level reset detected, delay do reset");
 		return true;
 	}
+
 	return false;
 }

--
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2024-03-05 17:39:33.616679088 +0800
+++ 0086-net-hns3-fix-VF-multiple-count-on-one-reset.patch	2024-03-05 17:39:30.833566495 +0800
@@ -1 +1 @@
-From 072a07a9dcbd604b1983bf2cb266d3dd4dc89824 Mon Sep 17 00:00:00 2001
+From 48d9241bbdfb813302c12f057b0d79d557856010 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 072a07a9dcbd604b1983bf2cb266d3dd4dc89824 ]
@@ -19 +21,0 @@
-Cc: stable at dpdk.org