patch 'net/axgbe: fix MAC TCR speed select field width' has been queued to stable release 24.11.5

[luca.boccassi at gmail.com]

Hi,

FYI, your patch has been queued to stable release 24.11.5

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 04/02/26. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/bluca/dpdk-stable

This queued commit can be viewed at:
https://github.com/bluca/dpdk-stable/commit/788155f3374a186365028fdfe0c788c7dd5eb0c1

Thanks.

Luca Boccassi

---
>From 788155f3374a186365028fdfe0c788c7dd5eb0c1 Mon Sep 17 00:00:00 2001
From: Ashok Kumar Natarajan <ashokkumar.natarajan at amd.com>
Date: Fri, 27 Mar 2026 17:50:03 +0530
Subject: [PATCH] net/axgbe: fix MAC TCR speed select field width

[ upstream commit 04c921fa73919a9b9cac5cbad5dd8d1f841c4508 ]

The MAC Transmit Configuration Register (TCR) speed select (SS)
field is defined as 2 bits wide, while the hardware specification
defines this field as 3 bits to encode all supported MAC speeds.

Update the SS field width to 3 bits to match the hardware
specification and avoid truncation of speed select values.

Fixes: 69e209be5464 ("net/axgbe: add register map and related macros")

Signed-off-by: Ashok Kumar Natarajan <ashokkumar.natarajan at amd.com>
---
 drivers/net/axgbe/axgbe_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 0e1b2c1500..0fe00d917a 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -488,7 +488,7 @@
 #define MAC_SSIR_SSINC_INDEX		16
 #define MAC_SSIR_SSINC_WIDTH		8
 #define MAC_TCR_SS_INDEX		29
-#define MAC_TCR_SS_WIDTH		2
+#define MAC_TCR_SS_WIDTH		3
 #define MAC_TCR_TE_INDEX		0
 #define MAC_TCR_TE_WIDTH		1
 #define MAC_TSCR_AV8021ASMEN_INDEX	28
-- 
2.47.3

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2026-03-31 22:26:26.147302005 +0100
+++ 0014-net-axgbe-fix-MAC-TCR-speed-select-field-width.patch	2026-03-31 22:26:24.906696634 +0100
@@ -1 +1 @@
-From 04c921fa73919a9b9cac5cbad5dd8d1f841c4508 Mon Sep 17 00:00:00 2001
+From 788155f3374a186365028fdfe0c788c7dd5eb0c1 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 04c921fa73919a9b9cac5cbad5dd8d1f841c4508 ]
+
@@ -14 +15,0 @@
-Cc: stable at dpdk.org
@@ -22 +23 @@
-index 0bceff5774..842077d972 100644
+index 0e1b2c1500..0fe00d917a 100644
@@ -25 +26 @@
-@@ -492,7 +492,7 @@
+@@ -488,7 +488,7 @@