[dpdk-test-report] |WARNING| pw99557 [PATCH] [v5] net/ice: add support for low Rx latency

dpdklab at iol.unh.edu dpdklab at iol.unh.edu
Wed Oct 6 15:14:07 CEST 2021


Test-Label: iol-testing
Test-Status: WARNING
http://dpdk.org/patch/99557

_apply patch failure_

Submitter: Alvin Zhang <alvinx.zhang at intel.com>
Date: Friday, September 24 2021 09:34:29 
Applied on: CommitID:2700326085033fd13339a8de31f58a95d1ee9c3f
Apply patch set 99557 failed:

Checking patch doc/guides/nics/ice.rst...
error: while searching for:

    -a af:00.0,pps_out='[pin:0]'

Driver compilation and testing
------------------------------


error: patch failed: doc/guides/nics/ice.rst:227
Checking patch drivers/net/ice/ice_ethdev.c...
error: while searching for:
#define ICE_PROTO_XTR_ARG         "proto_xtr"
#define ICE_HW_DEBUG_MASK_ARG     "hw_debug_mask"
#define ICE_ONE_PPS_OUT_ARG       "pps_out"

static const char * const ice_valid_args[] = {
	ICE_SAFE_MODE_SUPPORT_ARG,

error: patch failed: drivers/net/ice/ice_ethdev.c:30
error: while searching for:
	ICE_PROTO_XTR_ARG,
	ICE_HW_DEBUG_MASK_ARG,
	ICE_ONE_PPS_OUT_ARG,
	NULL
};


error: patch failed: drivers/net/ice/ice_ethdev.c:37
error: while searching for:
	if (ret)
		goto bail;

bail:
	rte_kvargs_free(kvlist);
	return ret;

error: patch failed: drivers/net/ice/ice_ethdev.c:1956
error: while searching for:
{
	struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
	uint32_t val, val_tx;
	int i;

	for (i = 0; i < nb_queue; i++) {
		/*do actual bind*/
		val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |

error: patch failed: drivers/net/ice/ice_ethdev.c:3272
error: while searching for:

		PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
			    base_queue + i, msix_vect);
		/* set ITR0 value */
		ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
		ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
		ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
	}

error: patch failed: drivers/net/ice/ice_ethdev.c:3283
error: while searching for:
			      ICE_HW_DEBUG_MASK_ARG "=0xXXX"
			      ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
			      ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
			      ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");

RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);

error: patch failed: drivers/net/ice/ice_ethdev.c:5497
Checking patch drivers/net/ice/ice_ethdev.h...
error: while searching for:
 * Cache devargs parse result.
 */
struct ice_devargs {
	int safe_mode_support;
	uint8_t proto_xtr_dflt;
	int pipe_mode_support;

error: patch failed: drivers/net/ice/ice_ethdev.h:476
Applying patch doc/guides/nics/ice.rst with 1 reject...
Rejected hunk #1.
Applying patch drivers/net/ice/ice_ethdev.c with 6 rejects...
Rejected hunk #1.
Rejected hunk #2.
Rejected hunk #3.
Rejected hunk #4.
Rejected hunk #5.
Rejected hunk #6.
Applying patch drivers/net/ice/ice_ethdev.h with 1 reject...
Rejected hunk #1.
diff a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst	(rejected hunks)
@@ -227,6 +227,18 @@ Runtime Config Options
 
     -a af:00.0,pps_out='[pin:0]'
 
+- ``Low Rx latency`` (default ``0``)
+
+  vRAN workloads require low latency DPDK interface for the front haul
+  interface connection to Radio. By specifying ``1`` for parameter
+  ``rx_low_latency``, each completed Rx descriptor can be written immediately
+  to host memory and the Rx interrupt latency can be reduced to 2us::
+
+    -a 0000:88:00.0,rx_low_latency=1
+
+  As a trade-off, this configuration may cause the packet processing performance
+  degradation due to the PCI bandwidth limitation.
+
 Driver compilation and testing
 ------------------------------
 
diff a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c	(rejected hunks)
@@ -30,6 +30,7 @@
 #define ICE_PROTO_XTR_ARG         "proto_xtr"
 #define ICE_HW_DEBUG_MASK_ARG     "hw_debug_mask"
 #define ICE_ONE_PPS_OUT_ARG       "pps_out"
+#define ICE_RX_LOW_LATENCY_ARG    "rx_low_latency"
 
 static const char * const ice_valid_args[] = {
 	ICE_SAFE_MODE_SUPPORT_ARG,
@@ -37,6 +38,7 @@
 	ICE_PROTO_XTR_ARG,
 	ICE_HW_DEBUG_MASK_ARG,
 	ICE_ONE_PPS_OUT_ARG,
+	ICE_RX_LOW_LATENCY_ARG,
 	NULL
 };
 
@@ -1956,6 +1958,9 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
 	if (ret)
 		goto bail;
 
+	ret = rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY_ARG,
+				 &parse_bool, &ad->devargs.rx_low_latency);
+
 bail:
 	rte_kvargs_free(kvlist);
 	return ret;
@@ -3272,8 +3277,9 @@ static int ice_init_rss(struct ice_pf *pf)
 {
 	struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 	uint32_t val, val_tx;
-	int i;
+	int rx_low_latency, i;
 
+	rx_low_latency = vsi->adapter->devargs.rx_low_latency;
 	for (i = 0; i < nb_queue; i++) {
 		/*do actual bind*/
 		val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
@@ -3283,8 +3289,21 @@ static int ice_init_rss(struct ice_pf *pf)
 
 		PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
 			    base_queue + i, msix_vect);
+
 		/* set ITR0 value */
-		ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
+		if (rx_low_latency) {
+			/**
+			 * Empirical configuration for optimal real time
+			 * latency reduced interrupt throttling to 2us
+			 */
+			ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);
+			ICE_WRITE_REG(hw, QRX_ITR(base_queue + i),
+				      QRX_ITR_NO_EXPR_M);
+		} else {
+			ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
+			ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0);
+		}
+
 		ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
 		ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
 	}
@@ -5497,7 +5516,8 @@ static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 			      ICE_HW_DEBUG_MASK_ARG "=0xXXX"
 			      ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
 			      ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
-			      ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
+			      ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
+			      ICE_RX_LOW_LATENCY_ARG "=<0|1>");
 
 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);
diff a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h	(rejected hunks)
@@ -476,6 +476,7 @@ struct ice_pf {
  * Cache devargs parse result.
  */
 struct ice_devargs {
+	int rx_low_latency;
 	int safe_mode_support;
 	uint8_t proto_xtr_dflt;
 	int pipe_mode_support;

https://lab.dpdk.org/results/dashboard/patchsets/18935/

UNH-IOL DPDK Community Lab


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