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<p class="MsoNormal"><span style="font-size:12.0pt">My guess is that most of the packet data has a short life in the L3 cache (before being overwritten by newer packets), but is never flushed to memory.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:12.0pt;color:black">From: </span></b><span style="font-size:12.0pt;color:black">Antonio Di Bacco <a.dibacco.ks@gmail.com><br>
<b>Date: </b>Wednesday, May 18, 2022 at 12:40 PM<br>
<b>To: </b>"users@dpdk.org" <users@dpdk.org><br>
<b>Subject: </b>DPDK performances surprise<o:p></o:p></span></p>
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<p class="MsoNormal">I recently read a performance test where l2fwd was able to receive packets (8000B) from a 100 Gbps card, swap the L2 addresses and send them back to the same port to be received by an ethernet analyzer. The throughput achieved was close
to 100 Gbps on a XEON machine (Intel(R) Xeon(R) Platinum 8176 CPU @ 2.10GHz) . This is the same processor I have and I know that, if I try to write around 8000B to the attached DDR4 (2666MT/s) on an allocated 1GB hugepage, I get a maximum throughput of around
20GB/s. <o:p></o:p></p>
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<p class="MsoNormal">Now, a 100 Gbps can generate a flow of around 12 GB/s, these packets have to be written to the DDR and then read back to swap L2 addresses and this leads to a cumulative bandwidth on the DDR that is around 2x12 GB/s and is more than the
20GB/s of available bandwidth on the DDR4. <o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">How can this be possible ? <o:p></o:p></p>
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