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<p class="MsoNormal"><span lang="EN-US">Hi experts,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">I had a traffic throughput test for my dpdk application, with same software and test case, only difference is the number of rx/tx descriptor:<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Rx/tx descriptor 512, test result 3.2mpps<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Rx/tx descriptor 2048, test result 3mpp<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">From perf data, rx descriptor 2048 case has more cache miss, and lower instruction per cycle<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Perf for 512 rx descriptor<o:p></o:p></span></p>
<p class="MsoNormal"><i><span lang="EN-US"> 114289237792 cpu-cycles<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 365408402395 instructions
<b> # 3.20 insn per cycle</b><o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 74186289932 branches<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 36020793 branch-misses # 0.05% of all branches<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 1298741388 bus-cycles<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 3413460 cache-misses
<b> # 0.723 % of all cache refs</b><o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 472363654 cache-references<o:p></o:p></span></i></p>
<p class="MsoNormal"><span lang="EN-US">Perf for 2048 rx descriptor:<o:p></o:p></span></p>
<p class="MsoNormal"><i><span lang="EN-US"> 57038451185 cpu-cycles<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 173805485573 instructions
<b># 3.05 insn per cycle</b><o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 35289607389 branches<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 15418885 branch-misses # 0.04% of all branches<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 648164239 bus-cycles<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 13170596 cache-misses
<b> # 1.702 % of all cache refs</b><o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span lang="EN-US"> 773765263 cache-references<o:p></o:p></span></i></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">I understand it means more rx descriptor somehow causes more cache miss and then less instruction per cycle, so lower performance.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Any one observe similar results?<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Any idea to mitigate (or investigate further) the impact? (we want to use 2048 to better tolerate some jitter/burst)<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Any comment?<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Thank you.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Br, Xiaoping<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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