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<p class="MsoNormal"><span lang="EN-US">Hi,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">I’m trying power saving feature in my server with intel sapphire rapid CPU. With “tsx=on” kernel parameter, I have both
<b>rtm</b> and <b>waitpkg</b> available in CPU flag.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">I tried rte_power_monitor_multi API to monitor on multiple address, but it never enters C0.2/C0.1 state.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">To find the reason I patched the code to return the transaction abort code as below:<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:10.5pt;mso-para-margin-left:1.0gd"><span lang="EN-US"> /* transaction abort, possible write to one of wait addresses */<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:10.5pt;mso-para-margin-left:1.0gd"><span lang="EN-US"> if (rc != RTE_XBEGIN_STARTED)<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:10.5pt;mso-para-margin-left:1.0gd"><span lang="EN-US">- return 0;<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:10.5pt;mso-para-margin-left:1.0gd"><span lang="EN-US">+ return rc;<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">and it turn out that RTM transaction always aborted with 0 (a few times with 4 or 6 also, which I think maybe expected due to memory change of monitored addresses).<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">I found some explanation of the abort state here:<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><a href="https://www.intel.com/content/www/us/en/develop/documentation/cpp-compiler-developer-guide-and-reference/top/compiler-reference/intrinsics/intrinsics-for-avx2/intrinsics-for-tsx/intrinsics-for-restrict-transactional-mem-ops/restricted-transactional-memory-overview.html">https://www.intel.com/content/www/us/en/develop/documentation/cpp-compiler-developer-guide-and-reference/top/compiler-reference/intrinsics/intrinsics-for-avx2/intrinsics-for-tsx/intrinsics-for-restrict-transactional-mem-ops/restricted-transactional-memory-overview.html</a><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">For abort code 0, it just say one example (CPUID used within transcation), but it seems CPUID is not used within rte_power_monitor_multi.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">I also tried rte_power_pause and rte_power_monitor, both works as expected, CPU enters C0.2 state (checked by
</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">perf stat --e r20ec -C xx</span><span lang="EN-US">)<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Now, I don’t know why the RTM transaction aborted with 0 and don’t know how to debug it.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Can anyone throw some light on this?<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Thank you.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Br, Xiaoping<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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