[dpdk-dev] [PATCH 5/5] testpmd: change some of testpmd default parameter to well tuned value

[Cunming Liang]

We usually use testpmd fwd to demostrate IO forwarding throughput.
For best throughput, it has to assign the special parameter to testpmd.
To makes it easier to run, now set it as defalut value.
Such parameters are MBUF Mempool Cache and RX/TX threshold registers.
    MBCACHE: 250
    RX threshold registers: pthresh=8 hthresh=8 wthresh=0
    TX threshold registers: pthresh=32 hthresh=0 wthresh=0

Signed-off-by: Cunming Liang <cunming.liang at intel.com>
Acked-by: Bruce Richardson <bruce.richardson at intel.com>
Acked-by: Yong Liu <yong.liu at intel.com>
Tested-by: Zhaochen Zhan <zhaochen.zhan at intel.com>
---
 app/test-pmd/testpmd.c | 6 +++---
 app/test-pmd/testpmd.h | 2 ++
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c
index 546d429..16fe596 100644
--- a/app/test-pmd/testpmd.c
+++ b/app/test-pmd/testpmd.c
@@ -174,7 +174,7 @@ uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT] = {
 uint8_t  tx_pkt_nb_segs = 1; /**< Number of segments in TXONLY packets */
 
 uint16_t nb_pkt_per_burst = DEF_PKT_BURST; /**< Number of packets per burst. */
-uint16_t mb_mempool_cache = DEF_PKT_BURST; /**< Size of mbuf mempool cache. */
+uint16_t mb_mempool_cache = DEF_MBUF_CACHE; /**< Size of mbuf mempool cache. */
 
 /* current configuration is in DCB or not,0 means it is not in DCB mode */
 uint8_t dcb_config = 0;
@@ -204,9 +204,9 @@ uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT; /**< Number of TX descriptors. */
  */
 #define RX_PTHRESH 8 /**< Default value of RX prefetch threshold register. */
 #define RX_HTHRESH 8 /**< Default value of RX host threshold register. */
-#define RX_WTHRESH 4 /**< Default value of RX write-back threshold register. */
+#define RX_WTHRESH 0 /**< Default value of RX write-back threshold register. */
 
-#define TX_PTHRESH 36 /**< Default value of TX prefetch threshold register. */
+#define TX_PTHRESH 32 /**< Default value of TX prefetch threshold register. */
 #define TX_HTHRESH 0 /**< Default value of TX host threshold register. */
 #define TX_WTHRESH 0 /**< Default value of TX write-back threshold register. */
 
diff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h
index 7e3beb6..6a9eab8 100644
--- a/app/test-pmd/testpmd.h
+++ b/app/test-pmd/testpmd.h
@@ -65,6 +65,8 @@ int main(int argc, char **argv);
 #define MAX_PKT_BURST 512
 #define DEF_PKT_BURST 32
 
+#define DEF_MBUF_CACHE 250
+
 #define CACHE_LINE_SIZE_ROUNDUP(size) \
 	(CACHE_LINE_SIZE * ((size + CACHE_LINE_SIZE - 1) / CACHE_LINE_SIZE))
 
-- 
1.8.1.4