[dpdk-dev] [PATCH v3 3/5] ixgbe: Config PFVML2FLT register
Thomas Monjalon
thomas.monjalon at 6wind.com
Thu Nov 6 14:57:19 CET 2014
Title would be more high level.
Example: "ixgbe: configure Rx mode for VMDQ"
2014-10-31 13:19, Ouyang Changchun:
> + for (i = 0; i < (int)num_pools; i++) {
> + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)
> + vmolr |= IXGBE_VMOLR_AUPE;
> + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)
> + vmolr |= IXGBE_VMOLR_ROMPE;
> + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)
> + vmolr |= IXGBE_VMOLR_ROPE;
> + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)
> + vmolr |= IXGBE_VMOLR_BAM;
> + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)
> + vmolr |= IXGBE_VMOLR_MPE;
> +
> + IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
> + }
Please factorize code with ixgbe_set_pool_rx_mode() which is really similar.
--
Thomas
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