[dpdk-dev] [PATCH v6 4/8] igb: add additional ieee1588 support functions
Pablo de Lara
pablo.de.lara.guarch at intel.com
Thu Nov 12 13:55:34 CET 2015
Add additional functions to support the existing IEEE1588
functionality and to enable getting, setting and adjusting
the device time.
Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod at intel.com>
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch at intel.com>
Reviewed-by: John McNamara <john.mcnamara at intel.com>
---
drivers/net/e1000/e1000_ethdev.h | 2 +
drivers/net/e1000/igb_ethdev.c | 202 +++++++++++++++++++++++++++++++++++++--
2 files changed, 194 insertions(+), 10 deletions(-)
diff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h
index a667a1a..5401277 100644
--- a/drivers/net/e1000/e1000_ethdev.h
+++ b/drivers/net/e1000/e1000_ethdev.h
@@ -33,6 +33,7 @@
#ifndef _E1000_ETHDEV_H_
#define _E1000_ETHDEV_H_
+#include <rte_time.h>
/* need update link, bit flag */
#define E1000_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
@@ -257,6 +258,7 @@ struct e1000_adapter {
struct e1000_vf_info *vfdata;
struct e1000_filter_info filter;
bool stopped;
+ struct rte_timecounter tc;
};
#define E1000_DEV_PRIVATE(adapter) \
diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index 2cb115c..ec2e79c 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -78,10 +78,11 @@
#define IGB_8_BIT_MASK UINT8_MAX
/* Additional timesync values. */
-#define E1000_ETQF_FILTER_1588 3
-#define E1000_TIMINCA_INCVALUE 16000000
-#define E1000_TIMINCA_INIT ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
- | E1000_TIMINCA_INCVALUE)
+#define E1000_CYCLECOUNTER_MASK 0xffffffffffffffff
+#define E1000_ETQF_FILTER_1588 3
+#define IGB_82576_TSYNC_SHIFT 16
+#define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
+#define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
#define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
static int eth_igb_configure(struct rte_eth_dev *dev);
@@ -236,6 +237,11 @@ static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
uint32_t flags);
static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
struct timespec *timestamp);
+static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
+static int igb_timesync_read_time(struct rte_eth_dev *dev,
+ struct timespec *timestamp);
+static int igb_timesync_write_time(struct rte_eth_dev *dev,
+ const struct timespec *timestamp);
static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
uint16_t queue_id);
static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
@@ -349,6 +355,9 @@ static const struct eth_dev_ops eth_igb_ops = {
.get_eeprom_length = eth_igb_get_eeprom_length,
.get_eeprom = eth_igb_get_eeprom,
.set_eeprom = eth_igb_set_eeprom,
+ .timesync_adjust_time = igb_timesync_adjust_time,
+ .timesync_read_time = igb_timesync_read_time,
+ .timesync_write_time = igb_timesync_write_time,
};
/*
@@ -4182,20 +4191,151 @@ eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
return 0;
}
+static uint64_t
+igb_read_cyclecounter(void *arg)
+{
+ struct rte_eth_dev *dev = (struct rte_eth_dev *) arg;
+ struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint64_t systime_cycles = 0;
+
+ switch (hw->mac.type) {
+ case e1000_i210:
+ case e1000_i211:
+ /*
+ * Need to read System Time Residue Register to be able
+ * to read the other two registers.
+ */
+ E1000_READ_REG(hw, E1000_SYSTIMR);
+ /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
+ systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
+ systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
+ * NSEC_PER_SEC;
+ break;
+ case e1000_82580:
+ case e1000_i350:
+ case e1000_i354:
+ /*
+ * Need to read System Time Residue Register to be able
+ * to read the other two registers.
+ */
+ E1000_READ_REG(hw, E1000_SYSTIMR);
+ systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
+ /* Only the 8 LSB are valid. */
+ systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
+ & 0xff) << 32;
+ break;
+ default:
+ systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
+ systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
+ << 32;
+ break;
+ }
+
+ return systime_cycles;
+}
+
+static void
+igb_start_cyclecounter(struct rte_eth_dev *dev)
+{
+ struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
+ uint32_t incval = 1;
+ uint32_t shift = 0;
+ uint64_t mask = E1000_CYCLECOUNTER_MASK;
+
+ switch (hw->mac.type) {
+ case e1000_82580:
+ case e1000_i350:
+ case e1000_i354:
+ /* 32 LSB bits + 8 MSB bits = 40 bits */
+ mask = (1ULL << 40) - 1;
+ /* fall-through */
+ case e1000_i210:
+ case e1000_i211:
+ /*
+ * Start incrementing the register
+ * used to timestamp PTP packets.
+ */
+ E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
+ break;
+ case e1000_82576:
+ incval = E1000_INCVALUE_82576;
+ shift = IGB_82576_TSYNC_SHIFT;
+ E1000_WRITE_REG(hw, E1000_TIMINCA,
+ E1000_INCPERIOD_82576 | incval);
+ break;
+ default:
+ /* Not supported */
+ return;
+ }
+
+ memset(&adapter->tc, 0, sizeof(struct rte_timecounter));
+ adapter->tc.read = igb_read_cyclecounter;
+ adapter->tc.cc_mask = mask;
+ adapter->tc.cc_shift = shift;
+ adapter->tc.arg = dev;
+}
+
+static int
+igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
+{
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
+
+ adapter->tc.nsec += delta;
+
+ return 0;
+}
+
+static int
+igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
+{
+ uint64_t ns;
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
+
+ ns = rte_timespec_to_ns(ts);
+
+ /* Reset the timecounter. */
+ rte_timecounter_init(&adapter->tc, ns);
+
+ return 0;
+}
+
+static int
+igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
+{
+ uint64_t ns;
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
+
+ ns = rte_timecounter_read(&adapter->tc);
+ *ts = rte_ns_to_timespec(ns);
+
+ return 0;
+}
+
static int
igb_timesync_enable(struct rte_eth_dev *dev)
{
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
uint32_t tsync_ctl;
uint32_t tsauxc;
+ uint64_t ns;
+ struct timespec zerotime = {0, 0};
/* Enable system time for it isn't on by default. */
tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
- /* Start incrementing the register used to timestamp PTP packets. */
- E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
+ /* Set 0.0 epoch time to initialize timecounter. */
+ ns = rte_timespec_to_ns(&zerotime);
+ igb_start_cyclecounter(dev);
+ rte_timecounter_init(&adapter->tc, ns);
/* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
@@ -4247,9 +4387,13 @@ igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
uint32_t flags __rte_unused)
{
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
+
uint32_t tsync_rxctl;
uint32_t rx_stmpl;
uint32_t rx_stmph;
+ uint64_t regival = 0;
tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
@@ -4257,9 +4401,26 @@ igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
+ rte_timecounter_read(&adapter->tc);
- timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
- timestamp->tv_nsec = 0;
+ switch (hw->mac.type) {
+ case e1000_82580:
+ case e1000_i350:
+ case e1000_i354:
+ regival = (uint64_t)((((uint64_t)(rx_stmph & 0xff)) << 32)
+ | rx_stmpl);
+ break;
+ case e1000_i210:
+ case e1000_i211:
+ regival = (uint64_t)((uint64_t)rx_stmph * NSEC_PER_SEC
+ + rx_stmpl);
+ break;
+ default:
+ regival = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
+ }
+
+ regival = rte_timecounter_cycles_to_ns_time(&adapter->tc, regival);
+ *timestamp = rte_ns_to_timespec(regival);
return 0;
}
@@ -4269,6 +4430,10 @@ igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
struct timespec *timestamp)
{
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
+ uint64_t regival = 0;
+
uint32_t tsync_txctl;
uint32_t tx_stmpl;
uint32_t tx_stmph;
@@ -4279,9 +4444,26 @@ igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
+ rte_timecounter_read(&adapter->tc);
+
+ switch (hw->mac.type) {
+ case e1000_82580:
+ case e1000_i350:
+ case e1000_i354:
+ regival = (uint64_t)((((uint64_t)(tx_stmph & 0xff)) << 32)
+ | tx_stmpl);
+ break;
+ case e1000_i210:
+ case e1000_i211:
+ regival = (uint64_t)((uint64_t)tx_stmph * NSEC_PER_SEC
+ + tx_stmpl);
+ break;
+ default:
+ regival = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
+ }
- timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
- timestamp->tv_nsec = 0;
+ regival = rte_timecounter_cycles_to_ns_time(&adapter->tc, regival);
+ *timestamp = rte_ns_to_timespec(regival);
return 0;
}
--
1.8.1.4
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