[dpdk-dev] [PATCH 1/2] aesni_mb: add counter mode support

Fan Zhang roy.fan.zhang at intel.com
Thu May 5 16:59:01 CEST 2016


This patch provides counter mode support to AES-NI multi-buffer library.

The following cipher algorithm is enabled:
- RTE_CRYPTO_CIPHER_AES_CTR

Signed-off-by: Fan Zhang <roy.fan.zhang at intel.com>
---
 doc/guides/cryptodevs/aesni_mb.rst             |  3 +++
 doc/guides/cryptodevs/overview.rst             |  6 +++---
 doc/guides/rel_notes/release_16_07.rst         |  5 +++++
 drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c     |  3 +++
 drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c | 20 ++++++++++++++++++++
 5 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/doc/guides/cryptodevs/aesni_mb.rst b/doc/guides/cryptodevs/aesni_mb.rst
index fd5414d..60a8914 100644
--- a/doc/guides/cryptodevs/aesni_mb.rst
+++ b/doc/guides/cryptodevs/aesni_mb.rst
@@ -48,6 +48,9 @@ Cipher algorithms:
 * RTE_CRYPTO_SYM_CIPHER_AES128_CBC
 * RTE_CRYPTO_SYM_CIPHER_AES192_CBC
 * RTE_CRYPTO_SYM_CIPHER_AES256_CBC
+* RTE_CRYPTO_SYM_CIPHER_AES128_CTR
+* RTE_CRYPTO_SYM_CIPHER_AES192_CTR
+* RTE_CRYPTO_SYM_CIPHER_AES256_CTR
 
 Hash algorithms:
 
diff --git a/doc/guides/cryptodevs/overview.rst b/doc/guides/cryptodevs/overview.rst
index e1f33e1..4a84146 100644
--- a/doc/guides/cryptodevs/overview.rst
+++ b/doc/guides/cryptodevs/overview.rst
@@ -55,9 +55,9 @@ Supported Cipher Algorithms
    "AES_CBC_128",x,,x,,
    "AES_CBC_192",x,,x,,
    "AES_CBC_256",x,,x,,
-   "AES_CTR_128",x,,,,
-   "AES_CTR_192",x,,,,
-   "AES_CTR_256",x,,,,
+   "AES_CTR_128",x,,x,,
+   "AES_CTR_192",x,,x,,
+   "AES_CTR_256",x,,x,,
    "SNOW3G_UEA2",x,,,,x
 
 Supported Authentication Algorithms
diff --git a/doc/guides/rel_notes/release_16_07.rst b/doc/guides/rel_notes/release_16_07.rst
index 84e61c0..4600e81 100644
--- a/doc/guides/rel_notes/release_16_07.rst
+++ b/doc/guides/rel_notes/release_16_07.rst
@@ -34,6 +34,11 @@ This section should contain new features added in this release. Sample format:
 
   Refer to the previous release notes for examples.
 
+* **Added AES-CTR support to AESNI MB PMD.**
+
+  Now AESNI MB PMD supports 128/192/256-bit counter mode AES encryption and
+  decryption.
+
 * **Added support of AES counter mode for Intel QuickAssist devices.**
 
   Enabled support for the AES CTR algorithm for IntelQuick Assist devices.
diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
index 3415ac1..ce763bf 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
@@ -222,6 +222,9 @@ aesni_mb_set_session_cipher_parameters(const struct aesni_mb_ops *mb_ops,
 	case RTE_CRYPTO_CIPHER_AES_CBC:
 		sess->cipher.mode = CBC;
 		break;
+	case RTE_CRYPTO_CIPHER_AES_CTR:
+		sess->cipher.mode = CNTR;
+		break;
 	default:
 		MB_LOG_ERR("Unsupported cipher mode parameter");
 		return -1;
diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c
index 3806a66..d3c46ac 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c
@@ -207,6 +207,26 @@ static const struct rte_cryptodev_capabilities aesni_mb_pmd_capabilities[] = {
 			}, }
 		}, }
 	},
+	{	/* AES CTR */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_CTR,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
-- 
2.5.5



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