[dpdk-dev] [PATCH v2 2/2] examples/performance-thread: add arm64 support

[Sekhar, Ashwin]

On Thu, 2017-05-18 at 14:25 +0530, Jerin Jacob wrote:
> -----Original Message-----
> > 
> > Date: Thu, 18 May 2017 00:34:26 -0700
> > From: Ashwin Sekhar T K <ashwin.sekhar at caviumnetworks.com>
> > To: jerin.jacob at caviumnetworks.com, john.mcnamara at intel.com,
> >  jianbo.liu at linaro.org
> > Cc: dev at dpdk.org, Ashwin Sekhar T K <ashwin.sekhar at caviumnetworks.c
> > om>
> > Subject: [dpdk-dev] [PATCH v2 2/2] examples/performance-thread: add
> > arm64
> >  support
> > X-Mailer: git-send-email 2.12.2
> > 
> > Updated Makefile to allow compilation for arm64 architecture.
> > 
> > Added necessary arm64 support for lthread.
> > 
> > Fixed minor compilation errors for arm64 compilation.
> > 
> > Tested the apps l3fwd-thread and lthread_pthread_shim on thunderx
> > and x86_64.
> > 
> > +void
> > +ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx
> > __rte_unused)
> > +{
> > +	/* SAVE CURRENT CONTEXT */
> > +	asm volatile (
> > +			/* Save SP */
> > +			"mov x3, sp\n"
> > +			"str x3, [x1, #0]\n"
> > +
> > +			/* Save FP and LR */
> > +			"stp x29, x30, [x1, #8]\n"
> > +
> > +			/* Save Callee Saved Regs x19 - x28 */
> > +			"stp x19, x20, [x1, #24]\n"
> > +			"stp x21, x22, [x1, #40]\n"
> > +			"stp x23, x24, [x1, #56]\n"
> > +			"stp x25, x26, [x1, #72]\n"
> > +			"stp x27, x28, [x1, #88]\n"
> > +		     );
> IMO, We need to save SIMD registers in the context as well.
> x86 code also not doing that, looks like it is an obvious bug in x86
> code as
> well.
> 
Yes. You are correct. Need to save the bottom 64-bits of called saved
ASIMD regs v8-v15. Will update the patch.